Level converting circuit

ABSTRACT

There is provided a level shifter in which short circuit current and the increase in delay are reduced when a firth power source is controlled. In a level shifter for converting a signal level of a first logic circuit to which a first power source is supplied into a signal level of a second logic circuit to which a second power source is supplied, the circuit has a configuration characterized by including a switching circuit between a GND power source terminal of a level shift core circuit and a GND power source, the switching circuit being controlled by a third logic circuit which generates a control signal under control of the first power source, and a pull-up/pull-down circuit at an output of the level shift core circuit, the pull-up and/or pull-down circuit being controlled by the third logic circuit.

TECHNICAL FIELD

The present invention relates to a level shifter, and in particular, toa level shifter in which a leakage current characteristic is improvedwhen a first power source is controlled.

RELATED ART

A level shifter is used in a system LSI including two or more powersources; for example, as shown in FIG. 1, there has been known a levelshifter proposed in Japanese application Laid-Open No. 63- 152220 and soon. Recently, to reduce the system LSI leakage current, it has beenrequired that the level shifter should deal with “off” of power supplyto unused blocks.

To deal with the requirement, it has been proposed, as disclosed in, forexample, U.S. Pat. No. 5,669,684, that a pull-down circuit is disposedon an output side of a level shifter to fix a p-MOS cross- coupled latchstate to thereby prevent the leakage current.

The technique disclosed by the article uses, as can be seen from FIG. 1of the article, a MOS including a drain terminal connected to the outputof a level shifter, a gate terminal connected to that of another outputof the level shifter, and a source terminal connected to GND.

PROBLEM TO BE SOLVED BY THE INVENTION

However, in the technique disclosed by the U.S. patent, when the firstpower source turns off and a level shift input signal is indefinite, thepull-down n-MOS is connected to the high state side of a p-MOScross-coupled latch of the level shifter and hence the gate terminalvoltage of the n-MOS possibly exceeds a threshold value of the n-MOS.

In this case, since a conduction path appears between the second powersource and a GND power source, there occurs a problem that short circuitcurrent flows.

Additionally, in a case in which the first power source turns on and aninput signal is inverted in a hold state, there exits a problem that theshort circuit current flows until the power source level increases to apredetermined level and the level shift output is completely changed.

Moreover, the additional n-MOS has a function to enhance the function ofthe level converter circuit to hold the state of the p-MOS cross-coupledlatch. Therefore, the level shift delay increases, particularly, whenthe potential difference between the first and second power sourcesbecomes large; the level shift margin is lost and hence the level shiftcannot be conducted. That is, there also occurs a problem that even theinput signal changes, the desired output cannot change.

It is a first object of the present invention to provide a level shifterin which occurrence of short circuit current can be suppressed even whenthe first power source is controlled and the increase in delay can alsobe suppressed in the level shift.

DISCLOSURE OF THE INVENTION

In accordance with the invention of a level shifter of claim 1, there isprovided a level shifter for converting a signal level of a first logiccircuit to which a first power source is supplied into a signal level ofa second logic circuit to which a second power source is supplied,characterized by including a switching circuit between a GND powersource terminal (ground power source terminal) of a level shift corecircuit and a GND power source (ground power source), the switchingcircuit being controlled by a third logic circuit which generatescontrol signals in accordance with control of the first power source,and a pull- up and/or pull-down circuit at an output of the level shiftcore circuit, the pull-up and/or pull-down circuit being controlled bythe third logic circuit.

In accordance with the invention of a level shifter of claim 2, there isprovided a level shifter for converting a signal level of a first logiccircuit to which a first power source is supplied into a signal level ofa second logic circuit to which a second power source is supplied,characterized by including a switching circuit between a power sourceterminal of a level shift core circuit and the second power source, theswitching circuit being controlled by a third logic circuit whichgenerates control signals in accordance with control of the first powersource, and a pull-up and/or pull-down circuit at outputs of the levelshift core circuit, the pull-up and/or pull-down circuit beingcontrolled by the third logic circuit.

In accordance with the invention of a level shifter of claim 3, thelevel shifter in claim 1 or 2 is characterized in that the level shiftcore circuit includes a p-MOS cross-coupled latch including at least twop- MOSs and a differential n-MOS including at least two n-MOSs; each ofthe p-MOSs includes a source terminal connected to the second powersource terminal and a gate terminal connected to a level shift outputwhich is each drain terminal; and each of the n-MOSs includes a sourceterminal connected to the GND power source terminal, a drain terminalconnected to the level shift output, and a gate terminal connected to alevel shift input.

In accordance with the invention of a level shifter of claim 4, thelevel shifter in claim 1 or 2 is characterized in that the level shiftcore circuit includes: a p-MOS cross-coupled latch including at leasttwo p- MOSs each of which includes a source terminal connected to thesecond power source and a gate terminal connected to each level shiftoutput; at least two p-MOSs switches in which a source terminal of theother p-MOS is connected to each drain terminal of the p-MOS, each gateterminal of the switches is connected to each level shift input, andeach drain terminal of the switches is connected to the level shiftoutput; and a differential n-MOS switch including at least two n-MOSseach of which includes a source terminal connected to the GND powersource terminal, a drain terminal connected to the level shift output,and a gate terminal connected to a level shift input.

In accordance with the invention of a level shifter of claim 5, thelevel shifter in claim 1 or 2 is characterized in that the pull-upand/or pull-down circuit is replaced with a pull-down circuit, thepull-down circuit including one n-MOS or at least two n-MOSs, each ofthe n- MOSs including a source connected to a GND power source, a gateterminal connected to an inverted signal of a control signal, and adrain terminal connected to at least one of the level shift outputs.

In accordance with the invention of a level shifter of claim 6, there isprovided a level shifter for converting a signal level of a first logiccircuit to which a first power source is supplied into a signal level ofa second logic circuit to which a second power source is supplied,characterized by including a pull-up and/or pull-down circuit in whichthe second power source is supplied to level shift outputs of a levelshift core circuit, a control circuit to which the second power sourceis supplied and which receives as inputs thereto a level shift inputsignal and the level shift output signal, and a switching circuit whichis disposed between a power source terminal of the level shift corecircuit and the second power source and which is controlled by a thirdlogic circuit, the third logic circuit generating control signals inaccordance with control of the first power source, wherein the controlcircuit is controlled by a control signal from the third logic circuit.

In accordance with the invention of a level shifter of claim 7, thelevel shifter in claim 6 is characterized in that the third logiccircuit controls the control circuit by control signals from the thirdlogic circuit, and the control circuit produces control signals tocontrol the pull-up and/or pull-down circuit and the level shift corecircuit.

In accordance with the invention of a level shifter of claim 8, thelevel shifter in claim 5 is characterized in that the control circuitfurther produces control signals to control the pull-up and/or pull-downcircuit to thereby control the pull-up and/or pull-down circuit.

In accordance with the invention of a level shifter of claim 9, thelevel shifter in claim 1, 3, or 6 is characterized in that the pull-upand/or pull-down circuit includes at least two p-MOSs each of whichincluding a source terminal connected to the second power source, a gateterminal connected to a control signal, and a drain terminal connectedto each of the level shift core outputs.

In accordance with the invention of a level shifter of claim 10, thelevel shifter in claim 1, 3, or 8 is characterized in that the pull-upand/or pull-down circuit comprises a p-MOS including a source terminalconnected to the second power source, a gate terminal connected to acontrol signal, and a drain terminal connected to one of the level shiftoutputs and an n-MOS including a source terminal connected to a GNDpower source, a gate terminal connected to an inverted signal of acontrol signal, and a drain terminal connected to other one of the levelshift outputs.

In accordance with the invention of a level shifter of claim 11, thereis provided a level shifter for converting a signal level of a firstlogic circuit to which a first power source is supplied into a signallevel of a second logic circuit to which a second power source issupplied, characterized by comprising a pull-down circuit at level shiftoutput signals of a level shift core circuit and a control circuit towhich the second power source is supplied and which receives as inputsthereto level shift input signals and the level shift output signals toproduce control signals for the pull-down circuit and the level shiftcore circuit, wherein the control circuit and the pull-down circuit arecontrolled by control signals from the third logic circuit.

In accordance with the invention of a level shifter of claim 12, thelevel shifter in claim 11 is characterized in that the NAND circuit isof a CMOS circuit configuration and the p-MOS transistor to which thelevel shift input signal is connected includes a transistor at leasthaving a small ratio of a channel width/a channel length or a highthreshold value.

In accordance with the invention of a level shifter of claim 13, thelevel shifter in claim 11 is characterized in that the NAND circuit isof a CMOS circuit configuration and the n-MOS transistor to which acontrol signal output of the third logic circuit is connected includes asource terminal connected to a GND power source.

In accordance with the invention of a level shifter of claim 14, thelevel shifter in claim 5 is characterized in that the pull-up and/orpull-down circuit includes at least two p-MOSs each of which includes asource terminal connected to the second power source and a gate terminalconnected to a control signal from the control circuit, each drainterminal of other p-MOS being connected to each of the level shiftoutputs; at least two n-MOSs each of which includes a source terminalconnected to the GND power source, a gate terminal connected to acontrol signal from the control circuit, and a drain terminal connectedto the level shift outputs; and additionally at least two p-MOSs each ofwhich includes a source terminal connected to the second power sourceand a gate terminal connected to a control signal from the third logiccircuit, a drain terminal of other p-MOS being connected to each of thelevel shift outputs.

In accordance with the invention of a level shifter of claim 15, thelevel shifter in claim 5 is characterized in that the pull-up and/orpull-down circuit includes at least two p-MOSs each of which includes asource terminal connected to the second power source and a gate terminalconnected to a control signal from the control circuit, each drainterminal of other p-MOS being connected to each of the level shiftoutputs; at least two n-MOSs each of which includes a source terminalconnected to the GND power source, a gate terminal connected to acontrol signal from the control circuit, and a drain terminal connectedto the level shift outputs; and additionally a p-MOS including a sourceterminal connected to the second power source, a gate terminal connectedto a control signal from the third logic circuit, a drain terminalconnected to one of the level shift outputs.

In accordance with the invention of a level shifter of claim 16, thelevel shifter in claim 7 is characterized in that the pull-up and/orpull-down circuit includes at least two p-MOSs each of which includes asource terminal connected to the second power source, a gate terminalconnected to a control signal from the control circuit, and a drainterminal connected to each of the level shift outputs; at least two n-MOSs each of which includes a source terminal connected to the GND powersource, a gate terminal connected to a control signal from the controlcircuit, and a drain terminal connected to the level shift outputs;additionally a p-MOS including a source terminal connected to the secondpower source, a gate terminal connected to a control signal from thethird logic circuit, and a drain terminal connected to one of the levelshift outputs; and additionally an n-MOS including a source terminalconnected to the GND power source, a gate terminal connected to acontrol signal from the third logic circuit or to an inverted signal ofthe control signal, and a drain terminal connected to other one of thelevel shift outputs.

In accordance with the invention of a level shifter of claim 17, thelevel shifter in claim 5 is characterized in that the pull-up and/orpull-down circuit includes at least two p-MOSs each of which includes asource terminal connected to the second power source and a gate terminalconnected to a control signal from the control circuit, a drain terminalof other p-MOS being connected to each of the level shift outputs; atleast two n-MOSs each of which includes a source terminal connected tothe GND power source, a gate terminal connected to a control signal fromthe control circuit, and a drain terminal connected to the level shiftoutputs; and additionally an n-MOS including a source terminal connectedto the GND power source, a gate terminal connected to a control signalfrom the third logic circuit or to an inverted signal of the controlsignal, and a drain terminal connected to one of the level shiftoutputs.

In accordance with the invention of a level shifter of claim 18, thelevel shifter in claim 5 is characterized in that the control circuitcomprises a NAND circuit to which the second power source is suppliedand which receives as inputs thereto a positively inverted signal of thelevel shift input signal, an inverted signal of the level shift outputsignal, and a control output of the third logic circuit and a NANDcircuit to which the second power source is supplied and which receivesas inputs thereto an inverted signal of the level shift input signal, apositively inverted signal of the level shift output signal, and acontrol output of the third logic circuit, wherein an output signal ofthe NAND circuit is produced as a control signal.

In accordance with the invention of a level shifter of claim 19, thelevel shifter in claim 18 is characterized in that the pull-up and/orpull-down circuit further includes at least two p-MOSs each of whichincludes a source terminal connected to the second power source and agate terminal connected to a control signal from the control circuit, adrain terminal of other p-MOS being connected to each of the level shiftoutputs; and additionally at least two p-MOSs each of which includes asource terminal connected to the second power source and a gate terminalconnected to a control signal from the third logic circuit, a drainterminal of other p-MOS being connected to each of the level shiftoutputs.

In accordance with the invention of a level shifter of claim 20, thelevel shifter in claim 18 is characterized in that the pull-up and/orpull-down circuit further includes at least two p-MOSs each of whichincludes a source terminal connected to the second power source, a gateterminal connected to a control signal from the control circuit, and adrain terminal connected to each of the level shift outputs; andadditionally a p-MOS including a source terminal connected to the secondpower source, a gate terminal connected to a control signal from thethird logic circuit, and a drain terminal connected to one of the levelshift outputs.

In accordance with the invention of a level shifter of claim 21, thelevel shifter in claim 18 is characterized in that the pull-up and/orpull-down circuit includes at least two p-MOSs each of which includes asource terminal connected to the second power source, a gate terminalconnected to a control signal from the control circuit, and a drainterminal connected to each of the level shift outputs; additionally a p-MOS including a source terminal connected to the second power source, agate terminal connected to a control signal from the third logiccircuit, and a drain terminal connected to one of the level shiftoutputs; and additionally an n-MOS including a source terminal connectedto the GND power source, a gate terminal connected to a control signalfrom the third logic circuit or to an inverted signal of the controlsignal, and a drain terminal connected to other one of the level shiftoutputs.

In accordance with the invention of a level shifter of claim 22, thelevel shifter in claim 18 is characterized in that the pull-up and/orpull-down circuit includes at least two p-MOSs each of which includes asource terminal connected to the second power source, a gate terminalconnected to a control signal from the control circuit, and a drainterminal connected to each of the level shift outputs; and additionallyan n-MOS including a source terminal connected to the GND power source,a gate terminal connected to a control signal from the third logiccircuit or an inverted signal of the control signal, and a drainterminal connected to one of the level shift outputs.

In accordance with the invention of a level shifter of claim 23, thelevel shifter in claim 5 is characterized in that the control circuitcomprises a NAND circuit to which the second power source is suppliedand which receives as inputs thereto a positively inverted signal of thelevel shift input signal, an inverted signal of the level shift outputsignal, and a control output of the third logic circuit, a NAND circuitto which the second power source is supplied and which receives asinputs thereto an inverted signal of the level shift input signal, apositively inverted signal of the level shift output, and a controloutput of the third logic circuit, and at least two inverters to whichthe second power source is supplied and which respectively receive asinputs thereto outputs from the NAND circuits, wherein each outputsignal from the inverters is produced as a control signal.

In accordance with the invention of a level shifter of claim 24, thelevel shifter in claim 18 is characterized in that the pull-up and/orpull-down circuit includes at least two n-MOSs each of which includes asource terminal connected to the GND power source, a gate terminalconnected to a control signal from the control circuit, and a drainterminal connected to the level shift outputs and additionally at leasttwo p-MOSs each of which includes a source terminal connected to thesecond power source and a gate terminal connected to a control signalfrom the third logic circuit, a drain terminal of other p-MOS beingconnected to each of the level shift outputs.

In accordance with the invention of a level shifter of claim 25, thelevel shifter in claim 23 is characterized in that the pull-up and/orpull-down circuit includes at least two n-MOSs each of which includes asource terminal connected to the GND power source, a gate terminalconnected to a control signal from the control circuit, and a drainterminal connected to the level shift outputs and additionally a p-MOSincluding a source terminal connected to the second power source, a gateterminal connected to a control signal from the third logic circuit, anda drain terminal connected to one of the level shift outputs.

In accordance with the invention of a level shifter of claim 26, thelevel shifter in claim 23 is characterized in that the pull-up and/orpull-down circuit includes at least two n-MOSs each of which includes asource terminal connected to the GND power source, a gate terminalconnected to a control signal from the control circuit, and a drainterminal connected to the level shift outputs; additionally a p-MOSincluding a source terminal connected to the second power source, a gateterminal connected to a control signal from the third logic circuit, anda drain terminal connected to one of the level shift outputs; andadditionally an n-MOS including a source terminal connected to the GNDpower source, a gate terminal connected to a control signal from thethird logic circuit or an inverted signal of the control signal, and adrain terminal connected to other one of the level shift outputs.

In accordance with the invention of a level shifter of claim 27, thelevel shifter in claim 23 is characterized in that the pull-up and/orpull-down circuit includes at least two n-MOSs each of which includes asource terminal connected to the GND power source, a gate terminalconnected to a control signal from the control circuit, and a drainterminal connected to the level shift outputs and additionally an n- MOSincluding a source terminal connected to the GND power source, a gateterminal connected to a control signal from the third logic circuit orto an inverted signal of the control signal, and a drain terminalconnected to other one of the level shift outputs.

In accordance with the invention of a level shifter of claim 28, thelevel shifter in claims 14 to 17 is characterized in that the controlcircuit comprises a NOR circuit to which the second power source issupplied and which receives as inputs thereto an inverted signal of thelevel shift input signal, a positively inverted signal of the levelshift output signal, and a control output of the third logic circuit oran inverted signal of the control output, a NOR circuit to which thesecond power source is supplied and which receives as inputs thereto apositively inverted signal of the level shift input signal, an invertedsignal of the level shift output, and a control output of the thirdlogic circuit or an inverted signal of the control output, and at leasttwo inverters to which the second power source is supplied and whichrespectively receive as inputs thereto outputs from the NOR circuits,wherein output signals respectively from the at least two NOR circuitsand the at least two inverters are produced as control signals.

In accordance with the invention of a level shifter of claim 29, thelevel shifter in claim 28 is characterized in that the NOR circuits areof a CMOS circuit configuration and a p-MOS to which the level shiftinput signal is connected includes a transistor at least having a smallratio of a channel width/a channel length or a threshold value which isof a negative polarity and which is a large absolute value.

In accordance with the invention of a level shifter of claim 30, thelevel shifter in claim 28 is characterized in that the NOR circuits areof a CMOS circuit configuration and a control signal from the thirdlogic circuit or an inverted signal thereof is connected to a p-MOS on apower source side.

In accordance with the invention of a level shifter of claim 31, thelevel shifter in claims 19 to 22 is characterized in that the controlcircuit comprises a NOR circuit to which the second power source issupplied and which receives as inputs thereto an inverted signal of thelevel shift input signal, a positively inverted signal of the levelshift output signal, and a control output of the third logic circuit oran inverted signal of the control output, a NOR circuit to which thesecond power source is supplied and which receives as inputs thereto apositively inverted signal of the level shift input signal, an invertedsignal of the level shift output, and a control output of the thirdlogic circuit or an inverted signal of the control output, and at leasttwo inverters to which the second power source is supplied and whichreceive as inputs thereto outputs from the respective NOR circuits,wherein each output signal from the inverters is produced as a controlsignal.

In accordance with the invention of a level shifter of claim 32, thelevel shifter in claims 24 to 27 is characterized in that the controlcircuit comprises a first NOR circuit to which the second power sourceis supplied and which receives as inputs thereto an inverted signal ofthe level shift input signal, a positively inverted signal of the levelshift output signal, and a control output of the third logic circuit oran inverted signal of the control output and a second NOR circuit towhich the second power source is supplied and which receives as inputsthereto a positively inverted signal of the level shift input signal, aninverted signal of the level shift output, and a control output of thethird logic circuit or an inverted signal of the control output, whereineach output signal from the first and second NOR circuits is produced asa control signal.

In accordance with the invention of a level shifter of claim 33, thelevel shifter in claim 6 is characterized in that the control circuitcomprises an AND-NOR circuit to which the second power source issupplied and which receives as inputs thereto a positively invertedsignal of the level shift input signal, an inverted signal of the levelshift output signal, and a control output of the third logic circuit oran inverted signal of the control output, a NAND circuit to which thesecond power source is supplied and which receives as inputs thereto aninverted signal of the level shift input signal, a positively invertedsignal of the level shift output, and a control output of the thirdlogic circuit, and at least two inverters to which the second powersource is supplied and which receive as inputs thereto outputs from therespective NAND circuits, wherein output signals from the AND-NORcircuit, the NAND circuit, and the inverters are produced as controlsignals.

In accordance with the invention of a level shifter of claim 34, thelevel shifter in claim 6 or 8 is characterized in that the pull-upand/or pull-down circuit includes at least two p-MOSs each of whichincludes a source terminal connected to the second power source and agate terminal connected to a control signal from the control circuit, adrain terminal of other p-MOS being connected to each of the level shiftoutputs and at least two n-MOSs each of which includes a source terminalconnected to the GND power source, a gate terminal connected to acontrol signal from the control circuit, and a drain terminal connectedto the level shift outputs.

In accordance with the invention of a level shifter of claim 35, thelevel shifter in claim 6 is characterized in that the control circuitcomprises an AND-NOR circuit to which the second power source issupplied and which receives as inputs thereto a positively invertedsignal of the level shift input signal, an inverted signal of the levelshift output signal, and a control output of the third logic circuit oran inverted signal of the control output and a NAND circuit to which thesecond power source is supplied and which receives as inputs thereto aninverted signal of the level shift input signal, a positively invertedsignal of the level shift output, and a control output of the thirdlogic circuit, wherein respective output signals from the AND-NORcircuit and the NAND circuit are produced as control signals.

In accordance with the invention of a level shifter of claim 36, thelevel shifter in claim 35 is characterized in that the pull-up and/orpull-down circuit includes at least two p-MOSs each of which includes asource terminal connected to the second power source and a gate terminalconnected to a control signal from the control circuit, a drain terminalof other p-MOS being connected to each of the level shift outputs.

In accordance with the invention of a level shifter of claim 37, thelevel shifter in claim 6 is characterized in that the control circuitcomprises an AND-NOR circuit to which the second power source issupplied and which receives as inputs thereto a positively invertedsignal of the level shift input signal, an inverted signal of the levelshift output signal, and a control output of the third logic circuit oran inverted signal of the control output, a NAND circuit to which thesecond power source is supplied and which receives as inputs thereto aninverted signal of the level shift input signal, a positively invertedsignal of the level shift output, and a control output of the thirdlogic circuit, and at least two inverters to which the second powersource is supplied and which receive as inputs thereto outputs from therespective NAND circuits, wherein each output signal from the invertersis produced as a control signal.

In accordance with the invention of a level shifter of claim 38, thelevel shifter in claim 37 is characterized in that the pull-up and/orpull-down circuit includes at least two n-MOSs each of which includes asource terminal connected to the GND power source, a gate terminalconnected to a control signal from the control circuit, and a drainterminal connected to the level shift outputs.

In accordance with the invention of a level shifter of claim 39, thelevel shifter in claim 34 is characterized in that the control circuitcomprises an OR-NAND circuit to which the second power source issupplied and which receives as inputs thereto an inverted signal of thelevel shift input signal, a positively inverted signal of the levelshift output signal, and a control output of the third logic circuit, aNOR circuit to which the second power source is supplied and whichreceives as inputs thereto a positively inverted signal of the levelshift input signal, an inverted signal of the level shift output, and acontrol output of the third logic circuit or an inverted signal of thecontrol output, and at least two inverters to which the second powersource is supplied and which receive as inputs thereto outputs from theeach of the NOR circuits, wherein each output signal from the OR-NANDcircuit, the NOR circuits, and the inverters is produced as a controlsignal.

In accordance with the invention of a level shifter of claim 40, thelevel shifter in claim 39 is characterized in that the OR-NAND circuitis of a CMOS circuit configuration and a p-MOS to which the level shiftinput signal is connected has at least one condition that the p-MOS hasa small ratio of a channel width/a channel length or a threshold valuewhich is of a negative polarity and which is a large absolute value.

In accordance with the invention of a level shifter of claim 41, thelevel shifter in claim 39 is characterized in that the OR-NAND circuitis of a CMOS circuit configuration and a control signal from the thirdlogic circuit is connected to an n-MOS on a GND power source side.

In accordance with the invention of a level shifter of claim 42, thelevel shifter in claim 36 is characterized in that the control circuitcomprises an OR-NAND circuit to which the second power source issupplied and which receives as inputs thereto an inverted signal of thelevel shift input signal, a positively inverted signal of the levelshift output signal, and a control output of the third logic circuit, aNOR circuit to which the second power source is supplied and whichreceives as inputs thereto a positively inverted signal of the levelshift input signal, an inverted signal of the level shift output, and acontrol output of the third logic circuit or an inverted signal of thecontrol output, and at least two inverters to which the second powersource is supplied and which receive as inputs thereto outputs from therespective NOR circuits, wherein each output signal from the invertersis produced as a control signal.

In accordance with the invention of a level shifter of claim 43, thelevel shifter in claim 38 is characterized in that the control circuitcomprises an OR-NAND circuit to which the second power source issupplied and which receives as inputs thereto an inverted signal of thelevel shift input signal, a positively inverted signal of the levelshift output signal, and a control output of the third logic circuit anda NOR circuit to which the second power source is supplied and whichreceives as inputs thereto a positively inverted signal of the levelshift input signal, an inverted signal of the level shift output, and acontrol output of the third logic circuit or an inverted signal of thecontrol output, wherein each output signal from the OR-NAND circuit andthe NOR circuit is produced as a control signal.

In accordance with the invention of a level shifter of claim 44, thelevel shifter in claim 36 is characterized in that the control circuitcomprises an AND-NOR circuit to which the second power source issupplied and which receives as inputs thereto a positively invertedsignal of the level shift input signal, an inverted signal of the levelshift output signal, and a control output of the third logic circuit oran inverted signal of the control output and an AND-NOR circuit to whichthe second power source is supplied and which receives as inputs theretoan inverted signal of the level shift input signal, a positivelyinverted signal of the level shift output, and a control output of thethird logic circuit or an inverted signal of the control output, whereineach output signal from the AND-NOR circuits is produced as a controlsignal.

In accordance with the invention of a level shifter of claim 45, thelevel shifter in claim 36 is characterized in that the control circuitcomprises an OR-NAND circuit to which the second power source issupplied and which receives as inputs thereto an inverted signal of thelevel shift input signal, a positively inverted signal of the levelshift output signal, and a control output of the third logic circuit, anOR- NAND circuit to which the second power source is supplied and whichreceives as inputs thereto a positively inverted signal of the levelshift input signal, an inverted signal of the level shift output, and acontrol output of the third logic circuit, and at least two inverters towhich the second power source is supplied and which receive as inputsthereto outputs from the respective OR-NAND circuits, wherein eachoutput signal from the inverters is produced as a control signal.

In accordance with the invention of a level shifter of claim 46, thelevel shifter in claim 38 is characterized in that the control circuitcomprises an AND-NOR circuit to which the second power source issupplied and which receives as inputs thereto a positively invertedsignal of the level shift input signal, an inverted signal of the levelshift output signal, and a control output of the third logic circuit oran inverted signal of the control output, an AND-NOR circuit to whichthe second power source is supplied and which receives as inputs theretoan inverted signal of the level shift input signal, a positivelyinverted signal of the level shift output, and a control output of thethird logic circuit or an inverted signal of the control output, and atleast two inverters to which the second power source is supplied andwhich receive as inputs thereto outputs from the respective AND-NORcircuits, wherein each output signal from the inverters is produced as acontrol signal.

In accordance with the invention of a level shifter of claim 47, thelevel shifter in claim 38 is characterized in that the control circuitcomprises an OR-NAND circuit to which the second power source issupplied and which receives as inputs thereto an inverted signal of thelevel shift input signal, a positively inverted signal of the levelshift output signal, and a control output of the third logic circuit andan OR-NAND circuit to which the second power source is supplied andwhich receives as inputs thereto a positively inverted signal of thelevel shift input signal, an inverted signal of the level shift output,and a control output of the third logic circuit, wherein each outputsignal from the OR-NAND circuits is produced as a control signal.

In accordance with the invention of a level shifter of claim 48, thelevel shifter in claim 47 is characterized in that the level shift corecircuit comprises a p-MOS cross-coupled latch including at least two ofthe p-MOS in which each source terminal is connected to the secondsource and a gate terminal of other p-MOS is connected to each of thelevel shift outputs, at least two p-MOS switches including a sourceterminal connected of a drain terminal of the p-MOS, each gate terminalconnected to a control signal from the control circuit, and each drainterminal connected to the level shift outputs, and a differential n-MOSswitch including at least two n-MOSs each of which includes a sourceterminal connected to a GND power source, a drain terminal connected tothe respective level shift outputs, and a gate terminal connected to alevel shift input.

In accordance with the invention of a level shifter of claim 49, thelevel shifter in claim one of claims 14 to 17, 19 to 22, and 24 to 27,characterized in that the control circuit comprises a first NAND circuitto which the second power source is supplied and which receives asinputs thereto a positively inverted signal of the level shift inputsignal, an inverted signal of the level shift output signal, and acontrol output of the third logic circuit, a second NAND circuit towhich the second power source is supplied and which receives as inputsthereto an inverted signal of the level shift input signal, a positivelyinverted signal of the level shift output, and a control output of thethird logic circuit, and at least two inverters to which the secondpower source is supplied and which receive as inputs thereto outputsfrom the respective NAND circuits, wherein each output signal from thefirst and second NAND circuits and the at least two inverters isproduced as a pull-up and/or pull-down control signal and each outputsignal of the inverters is produced as a control signal of the levelshift core circuit.

In accordance with the invention of a level shifter of claim 50, thelevel shifter in one of claims 14 to 17, 19 to 22, and 24 to 27,characterized in that the control circuit comprises a NOR circuit towhich the second power source is supplied and which receives as inputsthereto an inverted signal of the level shift input signal, a positivelyinverted signal of the level shift output signal, and a control outputof the third logic circuit or an inverted signal of the control output,a NOR circuit to which the second power source is supplied and whichreceives as inputs thereto a positively inverted signal of the levelshift input signal, an inverted signal of the level shift output, and acontrol output of the third logic circuit or an inverted signal of thecontrol output, and at least two inverters to which the second powersource is supplied and which respectively receive as inputs theretooutputs from the respective NOR circuits, wherein each output signalfrom the NOR circuits and the inverters is produced as a pull-up and/orpull-down control signal and each output signal of the NOR circuits isproduced as a control signal of the level shift core circuit.

In accordance with the invention of a level shifter of claim 51, thelevel shifter in claim one of claims 1, 3, and 6 to 9 characterized inthat the switching circuit comprises an n-MOS including a sourceterminal connected to a GND power source, a gate terminal connected to acontrol signal, and a drain terminal connected to a GND power sourceterminal of the level shift core circuit.

In accordance with the invention of a level shifter of claim 52, thelevel shifter in claim 34, characterized in that the control circuitcomprises an AND-NOR circuit to which the second power source issupplied and which receives as inputs thereto a positively invertedsignal of the level shift input signal, an inverted signal of the levelshift output signal, and a control output of the third logic circuit oran inverted signal of the control output, a NAND circuit to which thesecond power source is supplied and which receives as inputs thereto aninverted signal of the level shift input signal, a positively invertedsignal of the level shift output, and a control output of the thirdlogic circuit, and at least two inverters to which the second powersource is supplied and which receive as inputs thereto outputs from therespective NAND circuits, wherein each output signal from the AND- NORcircuit, the NAND circuit, and the at least two inverters is produced asa pull-up and/or pull-down control signal and each output signal of theinverters is produced as a control signal of the level shift corecircuit.

In accordance with the invention of a level shifter of claim 53, thelevel shifter in claim 39, characterized in that each output signal fromthe OR-NAND circuit, the NOR circuit, and the inverters is produced as apull-up and/or pull-down control signal and each output signal of theOR-NAND circuit and the NOR circuit is produced as a control signal ofthe level shift core circuit.

In accordance with the invention of a level shifter of claim 54, thelevel shifter in claim 8, characterized in that the control circuitcomprises a first AND-NOR circuit to which the second power source issupplied and which receives as inputs thereto a positively invertedsignal of the level shift input signal, an inverted signal of the levelshift output signal, and a control output of the third logic circuit oran inverted signal of the control output, a second AND-NOR circuit towhich the second power source is supplied and which receives as inputsthereto an inverted signal of the level shift input signal, a positivelyinverted signal of the level shift output, and a control output of thethird logic circuit or an inverted signal of the control output, and atleast two inverters to which the second power source is supplied andwhich receive as inputs thereto outputs from the first and secondAND-NOR circuits, wherein each output signal from the first and secondAND-NOR circuits is produced as a pull-up and/or pull-down controlsignal and each output signal of the inverters is produced as a controlsignal of the level shift core circuit, and the pull-up and/or pull-downcircuit includes at least two p-MOSs each of which includes a sourceterminal connected to the second power source and a gate terminalconnected to a control signal from the control circuit, a drain terminalof other p-MOS being connected to each of the level shift outputs.

In accordance with the invention of a level shifter of claim 55, thelevel shifter in claim 8, characterized in that the control circuitcomprises a first OR-NAND circuit to which the second power source issupplied and which receives as inputs thereto an inverted signal of thelevel shift input signal, a positively inverted signal of the levelshift output signal, and a control output of the third logic circuit, asecond OR-NAND circuit to which the second power source is supplied andwhich receives as inputs thereto a positively inverted signal of thelevel shift input signal, an inverted signal of the level shift output,and a control output of the third logic circuit, and at least twoinverters to which the second power source is supplied and which receiveas inputs thereto outputs from the first and second OR-NAND circuits,wherein each output signal from the at least two inverters is producedas a pull-up and/or pull-down control signal and each output signal fromthe OR-NAND circuits is produced as a control signal of the level shiftcore circuit, and the pull-up and/or pull-down circuit includes at leasttwo p-MOSs each of which includes a source terminal connected to thesecond power source and a gate terminal connected to a control signalfrom the control circuit, a drain terminal of other p-MOS beingconnected to each of the level shift outputs.

In accordance with the invention of a level shifter of claim 56, thelevel shifter in one of claims 4 to 7 and 9 to 11, characterized in thatthe control circuit comprises an AND-NOR circuit to which the secondpower source is supplied and which receives as inputs thereto apositively inverted signal of the level shift input signal, an invertedsignal of the level shift output signal, and a control output of thethird logic circuit or an inverted signal of the control output, anAND-NOR circuit to which the second power source is supplied and whichreceives as inputs thereto an inverted signal of the level shift inputsignal, a positively inverted signal of the level shift output, and acontrol output of the third logic circuit or an inverted signal of thecontrol output, and at least two inverters to which the second powersource is supplied and which receive as inputs thereto outputs from therespective AND-NOR circuits, wherein each output signal from theinverters is produced as a pull-up and/or pull-down control signal, eachoutput signal from the inverters is produced as a control signal of thelevel shift core circuit, and the pull-up and/or pull-down circuitincludes at least two n-MOS each of which includes a source terminalconnected to the GND power source, a gate terminal connected to acontrol signal from the control circuit, and a drain terminal connectedto the level shift outputs.

In accordance with the invention of a level shifter of claim 57, thelevel shifter in one of claims 4 to 7 and 9 to 11, characterized in thatthe control circuit comprises a first OR-NAND circuit to which thesecond power source is supplied and which receives as inputs thereto aninverted signal of the level shift input signal, a positively invertedsignal of the level shift output signal, and a control output of thethird logic circuit and a second OR-NAND circuit to which the secondpower source is supplied and which receives as inputs thereto apositively inverted signal of the level shift input signal, an invertedsignal of the level shift output, and a control output of the thirdlogic circuit, wherein each output signal from the first and secondOR-NAND circuits is produced as a pull-up and/or pull-down controlsignal, each output signal from the OR-NAND circuits is produced as acontrol signal of the level shift core circuit, and the pull-up and/orpull-down circuit includes at least two n-MOSs each of which includes asource terminal connected to the GND power source, a gate terminalconnected to a control signal from the control circuit, and a drainterminal connected to the level shift outputs.

In accordance with the invention of a level shifter of claim 58, thelevel shifter in one of claims 4 to 7 and 9 to 11, characterized in thatthe control circuit comprises an AND-NOR circuit to which the secondpower source is supplied and which receives as inputs thereto apositively inverted signal of the level shift input signal, an invertedsignal of the level shift output signal, and a control output of thethird logic circuit or an inverted signal of the control output, anAND-NOR circuit to which the second power source is supplied and whichreceives as inputs thereto an inverted signal of the level shift inputsignal, a positively inverted signal of the level shift output, and acontrol output of the third logic circuit or an inverted signal of thecontrol output, and at least two inverters to which the second powersource is supplied and which receive as inputs thereto outputs from therespective AND-NOR circuits, wherein each output signal of the invertersis produced as a control signal of the level shift core circuit.

In accordance with the invention of a level shifter of claim 59, thelevel shifter in one of claims 4 to 7 and 9 to 11, characterized in thatthe control circuit comprises an OR-NAND circuit to which the secondpower source is supplied and which receives as inputs thereto aninverted signal of the level shift input signal, a positively invertedsignal of the level shift output signal, and a control output of thethird logic circuit and an OR-NAND circuit to which the second powersource is supplied and which receives as inputs thereto a positivelyinverted signal of the level shift input signal, an inverted signal ofthe level shift output, and a control output of the third logic circuit,wherein each output signal from the OR-NAND circuits is produced as acontrol signal of the level shift core circuit.

In accordance with the invention of a level shifter of claim 60, thelevel shifter in one of claims 1, 3, 10, 59 and 60, characterized inthat: the level shift core circuit comprises a p-MOS cross-coupled latchincluding at least two first p-MOS, a differential n-MOS including atleast two n-MOSs, and at least two second p-MOS, wherein: the p- MOScross-coupled latch includes a source terminal connected to the secondpower source and a gate terminal connected to a level shift output whichis each drain terminal; the differential n-MOS includes each sourceterminal connected to the GND power source, each drain terminalconnected to the level shift output, and each gate terminal connected toa level shift input; and the second p-MOS includes each drain terminalconnected to the second power source, each gate terminal connected tothe level shift input, and each source terminal connected to the levelshift output.

In accordance with the invention of a level shifter of claim 61, thereis provided a level shifter for converting a signal level of a firstlogic circuit to which a first power source is supplied into a signallevel of a second logic circuit to which a second power source issupplied, characterized by including a pull-down circuit at level shiftoutputs of a level shift core circuit and a control circuit to which thesecond power source is supplied and which receives as inputs theretolevel shift input signals and the level shift output signals to producecontrol signals for a pull-down circuit and a level shift core circuit,wherein the control circuit is also connected to control signals fromthe third logic circuit.

In accordance with the invention of a level shifter of claim 62, thelevel shifter in claim 61, characterized in that the control circuit,the control circuit comprises a first OR-NAND circuit to which thesecond power source is supplied and which receives as inputs thereto aninverted signal of the level shift input signal, a positively invertedsignal of the level shift output signal, and a control output of thethird logic circuit and a second OR-NAND circuit to which the secondpower source is supplied and which receives as inputs thereto apositively inverted signal of the level shift input signal, an invertedsignal of the level shift output, and a control output of the thirdlogic circuit, wherein each output signal from the first and secondOR-NAND circuits is produced as a pull-up and/or pull-down controlsignal, each output signal from the OR-NAND circuits is produced as acontrol signal of the level shift core circuit, and the pull-downcircuit, the pull- up and/or pull-down circuit include at least twon-MOSs each of which includes a source terminal connected to the GNDpower source, a gate terminal connected to a control signal from thecontrol circuit, and a drain terminal connected to the level shiftoutputs.

In accordance with the invention of a level shifter of claim 63, thelevel shifter in claim 61, characterized in that the control circuit,the control circuit comprises a first OR-NAND circuit to which thesecond power source is supplied and which receives as inputs thereto aninverted signal of the level shift input signal, a positively invertedsignal of the level shift output signal, and a control output of thethird logic circuit and a second OR-NAND circuit to which the secondpower source is supplied and which receives as inputs thereto apositively inverted signal of the level shift input signal, an invertedsignal of the level shift output, and a control output of the thirdlogic circuit or an inverted signal of the control output, wherein eachoutput signal from the first and second OR-NAND circuits is produced asa pull-up and/or pull-down control signal, each output signal from theOR-NAND circuits is produced as a control signal of the level shift corecircuit, and the pull-down circuit, the pull-up and/or pull-down circuitinclude at least two n-MOSs each of which includes a source terminalconnected to the GND power source, a gate terminal connected to acontrol signal from the control circuit, and a drain terminal connectedto the level shift outputs.

In accordance with the invention of a level shifter of claim 64, thelevel shifter in one of claims 2, 7 to 9, and 61, characterized in thatthe switching circuit comprises a p-MOS including a source terminalconnected to the second power source, a gate terminal connected to acontrol signal or an inverted signal thereof, and a drain terminalconnected to a power source terminal of the level shift core circuit.

In accordance with the invention of a level shifter of claim 65, thelevel shifter in one of claims 3, 5, 6, and 61, characterized in thatthe control circuit comprises at least two NOR circuits to which thesecond power source is supplied and which receives as inputs thereto aninverted signal of the level shift input signal, a positively invertedsignal of the level shift output signal, and a control output of thethird logic circuit or an inverted signal of the control output and aNOR circuit to which the second power source is supplied and whichreceives as inputs thereto a positively inverted signal of the levelshift input signal, an inverted signal of the level shift output, and acontrol output of the third logic circuit or an inverted signal of thecontrol output, wherein each output signal from the NOR circuits isproduced as a control signal of the level shift core circuit.

In accordance with the invention of a level shifter of claim 66, thelevel shifter in one of claims 3, 11, 12, and 61, characterized in thatthe control circuit comprises at least two NAND circuits to which thesecond power source is supplied and which receives as inputs thereto apositively inverted signal of the level shift input signal, an invertedsignal of the level shift output signal, and a control output of thethird logic circuit, a NAND circuit to which the second power source issupplied and which receives as inputs thereto an inverted signal of thelevel shift input signal, a positively inverted signal of the levelshift output signal, and a control output of the third logic circuit,and at least two inverters to which the second power source is suppliedand which receives as inputs thereto outputs from the respective NANDcircuits, wherein each output signal from the inverters is produced as acontrol signal of the level shift core circuit.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a circuit diagram showing an example of a conventional levelshifter.

FIG. 2 is a circuit diagram showing an example of a conventional levelshifter.

FIG. 3 is a circuit diagram showing an example of a conventional levelshifter.

FIG. 4 is a circuit diagram showing a configuration example in a firstembodiment of a level shifter of the present invention.

FIG. 5 is a circuit diagram showing an example of a level shift corecircuit used in the first embodiment and so on.

FIG. 6 is a circuit diagram showing another example of a level shiftcore circuit used in the first embodiment and so on.

FIG. 7 is a circuit diagram showing an example of a switching circuitused in the first embodiment and so on.

FIG. 8 is a circuit diagram showing an example of a pull- up/pull-downcircuit used in the first embodiment and so on.

FIG. 9 is a timing chart showing an operation example of a level shiftcore circuit section of the present invention.

FIG. 10 is a timing chart showing an operation example of the firstembodiment of the level shift core circuit section of the presentinvention.

FIG. 11 is a circuit diagram showing another example of a pull-up/pull-down circuit used in the first embodiment and so on.

FIG. 12 is a circuit diagram showing further another example of apull-up/pull-down circuit used in the first embodiment and so on.

FIG. 13 is a circuit diagram showing still another example of apull-up/pull-down circuit used in the first embodiment and so on.

FIG. 14 is a circuit diagram showing another example of a level shiftcore circuit used in the first embodiment and so on.

FIG. 15 is a circuit diagram showing another example of FIG. 12 of alevel shift core circuit used in the first embodiment and so on.

FIG. 16 is a circuit diagram showing another example of a level shiftcore circuit used in the first embodiment and so on.

FIG. 17 is a circuit diagram showing another example of FIG. 13 of alevel shift core circuit used in the first embodiment and so on.

FIG. 18 is a circuit diagram showing further another example of a levelshift core circuit used in the first embodiment and so on.

FIG. 19 is a circuit diagram showing another example of FIG. 15 of alevel shift core circuit used in the first embodiment and so on.

FIG. 20 is a circuit diagram showing a configuration example in a secondembodiment of a level shifter of the present invention.

FIG. 21 is a circuit diagram showing an example of a level shift corecircuit used in the second embodiment and so on.

FIG. 22 is a circuit diagram showing an example of a pull-down circuitused in the second embodiment and so on.

FIG. 23 is a circuit diagram showing another example of a pull- downcircuit used in the second embodiment and so on.

FIG. 24 is a circuit diagram showing a configuration example in a thirdembodiment of a level shifter of the present invention.

FIG. 25 is a circuit diagram showing an example of a control circuitused in the third embodiment and so on.

FIG. 26 is a circuit diagram showing an example of a pull- up/pull-downcircuit used in the third embodiment and so on.

FIG. 27 is a circuit diagram showing an example of a NAND circuitconstituting a control circuit used in the third embodiment and so on.

FIG. 28 is a timing chart showing an operation example of the thirdembodiment of the level shift core circuit of the present invention.

FIG. 29 is a circuit diagram showing another example of a pull-up/pull-down circuit used in the third embodiment and so on.

FIG. 30 is a circuit diagram showing further another example of apull-up/pull-down circuit used in the third embodiment and so on.

FIG. 31 is a circuit diagram showing still another example of apull-up/pull-down circuit used in the third embodiment and so on.

FIG. 32 is a circuit diagram showing another example of a controlcircuit used in the third embodiment and so on.

FIG. 33 is a circuit diagram showing an example of a pull- up/pull-downcircuit used in the third embodiment and so on.

FIG. 34 is a circuit diagram showing another example of a pull-up/pull-down circuit used in the third embodiment and so on.

FIG. 35 is a circuit diagram showing further another example of apull-up/pull-down circuit used in the third embodiment and so on.

FIG. 36 is a circuit diagram showing still another example of apull-up/pull-down circuit used in the third embodiment and so on.

FIG. 37 is a circuit diagram showing an example of a level shift corecircuit used in a fifth embodiment and so on.

FIG. 38 is a circuit diagram showing another example of a controlcircuit used in the third embodiment and so on.

FIG. 39 is a circuit diagram showing still another example of apull-up/pull-down circuit used in the third embodiment and so on.

FIG. 40 is a circuit diagram showing still another example of apull-up/pull-down circuit used in the third embodiment and so on.

FIG. 41 is a circuit diagram showing still another example of apull-up/pull-down circuit used in the third embodiment and so on.

FIG. 42 is a circuit diagram showing still another example of apull-up/pull-down circuit used in the third embodiment and so on.

FIG. 43 is a circuit diagram showing further another example of acontrol circuit used in the third embodiment and so on.

FIG. 44 is a circuit diagram showing still another example of a controlcircuit used in the third embodiment and so on.

FIG. 45 is a circuit diagram showing still another example of a controlcircuit used in the third embodiment and so on.

FIG. 46 is a circuit diagram showing another example of a NOR circuitconstituting a control circuit used in the third embodiment and so on.

FIG. 47 is a configuration diagram showing a configuration example in afourth embodiment of a level shifter of the present invention.

FIG. 48 is a circuit diagram showing an example of a control circuitused in the fourth embodiment and so on.

FIG. 49 is a circuit diagram showing an example of a pull- up/pull-downcircuit used in the fourth embodiment and so on.

FIG. 50 is a circuit diagram showing an example of an AND-NOR circuitconstituting a control circuit used in the fourth embodiment and so on.

FIG. 51 is a timing chart showing an operation example of the levelshift core circuit of the fourth embodiment.

FIG. 52 is a circuit diagram showing another example of a controlcircuit used in the fourth embodiment and so on.

FIG. 53 is a circuit diagram showing another example of a pull-up/pull-down circuit used in the fourth embodiment and so on.

FIG. 54 is a circuit diagram showing another example of a controlcircuit used in the fourth embodiment and so on.

FIG. 55 is a circuit diagram showing another example of a pull-up/pull-down circuit used in the fourth embodiment and so on.

FIG. 56 is a circuit diagram showing another example of a controlcircuit used in the fourth embodiment and so on.

FIG. 57 is a circuit diagram showing further another example of acontrol circuit used in the fourth embodiment and so on.

FIG. 58 is a circuit diagram showing still another example of a controlcircuit used in the fourth embodiment and so on.

FIG. 59 is a circuit diagram showing an example of an OR-NAND circuitconstituting a control circuit used in the fourth embodiment and so on.

FIG. 60 is a circuit diagram showing still another example of a controlcircuit used in the fourth embodiment and so on.

FIG. 61 is a circuit diagram showing still another example of a controlcircuit used in the fourth embodiment and so on.

FIG. 62 is a circuit diagram showing another example of a controlcircuit used in the fourth embodiment and so on.

FIG. 63 is a circuit diagram showing still another example of a controlcircuit used in the fourth embodiment and so on.

FIG. 64 is a diagram showing a configuration example of a fifthembodiment of a level shifter of the present invention.

FIG. 65 is a circuit diagram showing an example of a level shift corecircuit used in the fifth embodiment and so on.

FIG. 66 is a circuit diagram showing an example of a control circuitused in the fifth embodiment and so on.

FIG. 67 is a circuit diagram showing another example of a controlcircuit used in the fifth embodiment and so on.

FIG. 68 is a circuit diagram showing still another example of a controlcircuit used in the fifth embodiment and so on.

FIG. 69 is a circuit diagram showing still another example of a controlcircuit used in the fifth embodiment and so on.

FIG. 70 is a circuit diagram showing still another example of a controlcircuit used in the fifth embodiment and so on.

FIG. 71 is a circuit diagram showing still another example of a controlcircuit used in the fifth embodiment and so on.

FIG. 72 is a circuit diagram showing still another example of a controlcircuit used in the fifth embodiment and so on.

FIG. 73 is a circuit diagram showing still another example of a controlcircuit used in the fifth embodiment and so on.

FIG. 74 is a diagram showing a configuration example of a sixthembodiment of a level shifter of the present invention.

FIG. 75 is a circuit diagram showing an example of a control circuitused in the sixth embodiment and so on.

FIG. 76 is a circuit diagram showing another example of a controlcircuit used in the sixth embodiment and so on.

FIG. 77 is a circuit diagram showing another example of a controlcircuit used in the sixth embodiment and so on.

FIG. 78 is a circuit diagram showing still another example of a controlcircuit used in the sixth embodiment and so on.

FIG. 79 is a circuit diagram showing still another example of a controlcircuit used in the sixth embodiment and so on.

FIG. 80 is a circuit diagram showing still another example of a controlcircuit used in the sixth embodiment and so on.

FIG. 81 is a circuit diagram showing still another example of a controlcircuit used in the sixth embodiment and so on.

FIG. 82 is a circuit diagram showing still another example of a controlcircuit used in the sixth embodiment and so on.

FIG. 83 is a diagram showing a configuration example of a seventhembodiment of a level shifter of the present invention.

FIG. 84 is a diagram showing another configuration example of theseventh embodiment of a level shifter of the present invention.

FIG. 85 is a timing chart showing an operation example of the levelshifter of the seventh embodiment.

Incidentally, reference numeral 1 is a level shift core circuit.Reference numeral 2 is a control circuit. Reference numeral 3 is apull-up/pull-down circuit. Reference numeral 3-1 is a pull-up circuit.Reference numeral 3-2 is a pull-down circuit. Reference numeral 10 is aswitching circuit. Reference numeral 11 is a first logic circuit.Reference numeral 12 is a second logic circuit. Reference numeral 13 isa third logic circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

Referring to the accompanying drawings, description will be given indetail of an embodiment of the present invention.

The level shifter of the present invention is characterized in that aswitching circuit controlled by a control signal is disposed between aGND power source terminal of a level shift core circuit and a GND powersource, and a pull-up and/or pull-down circuit controlled by a controlsignal is connected to a level shift output.

Each of the switching circuit and the pull-up and/or pull-down circuitconducts an operation (function) in which to control a first powersource, each of the circuit exclusively turns off (on); and to turn thefirst power source off, each of the circuit prevents short circuitcurrent and fixes a level shift output signal. There are hence obtainedadvantages of reliable suppression of the short circuit current andsuppression of the delay increase in the level shift.

First Embodiment

FIG. 4 shows an embodiment of a level converter circuit of the presentinvention.

The level converter circuit converts a signal level of a first logiccircuit 11 supplied with a first power source (VDDL) into a signal levelof a second logic circuit 12 supplied with a second power source (VDDH),and the level converter includes a level shift core circuit 1.

A signal (data; INL,INLB) at the first power source level is fed fromthe first logic circuit 11 to the core circuit 1 to be converted into asignal at the second power source level (the level shift output isindicated by OUTH,OUTHB in FIG. 4).

Moreover, in the first embodiment of the level converter in accordancewith the present invention, a switching circuit 10 controlled by acontrol signal (E0) from a third logic circuit and a pull-up and/orpull-down circuit 3 connected to a level shift output and controlled bya control signal (E1) from the third logic circuit 13 are disposedbetween a GND power source terminal of the core circuit 1 and a GNDpower source. To control the first power source (VDDL), the switchingcircuit 10 and the pull-up and/or pull-down circuit 3 are controlled bythe third logic circuit 13; to turn the first power source (VDDL) off,the switching circuit 10 is beforehand turned off and the pull-up and/orpull-down circuit 3 is turned on to prevent short circuit current and todetermine a level shift output signal when the level shift input isindefinite. Additionally, to turn the first power source (VDDL) on, whenthe first power source and the level shift input are stabilizedthereafter, the pull-up and/or pull-down circuit 3 is turned off and theswitching circuit 10 is turned on to conduct the level shift. The levelshift output signal (OUTH, OUTHB) thus obtained is supplied to thesecond logic circuit 12.

FIG. 5 shows a configuration example of a level shift core circuit 1used in the level converter of FIG. 4. That is, the level shift corecircuit 1 used in the embodiment includes at least two p-MOSs (p-MOStransistors; to be simply referred to as p-MOS hereinbelow; n-MOStransistors are similarly referred to as n-MOS) 1101 whose sourceterminals are connected to a second power source (VDDH) and whose drainterminals respectively connected to level shift outputs (OUTHB, OUTH)are connected in cross-coupled connection and n-MOS 1102 whose drainterminals are respectively connected to the level shift outputs (OUTHB,OUTH), whose gate terminal is connected to INL, and whose sourceterminals are connected to a GND power source terminal 111. FIG. 5 showsa circuit diagram in which the GND power source side 1111 on the sourceside of the n-MOS 1102 is shared therebetween. FIG. 6 shows a circuitdiagram in which the GND power source side 1111 on the source side ofthe n-MOS 1102 is independently wired.

In the configuration of the switching circuit 10 shown in FIG. 7 andused in the level converter of FIG. 4, the GND power source terminalside of the switching circuit 10 shown in FIG. 7 is independently (inparallel) connected to independent wires of the GND side on the sourceside of the n-MOS in FIG. 6. That is, while one switching circuit isdisposed in FIG. 5, two (or more) switching circuits are connected inparallel to each n-MOS of the core circuit 1, and the source side of then-MOS 101-1 is connected to GND (ground) in the level shift core circuit1 shown in FIG. 6. In this situation, the connection 1112 to the n-MOS101-1 of the switching circuit can be separately conducted or can beconducted after a common connection is established (wiring lines areconnected into one common connection wiring line).

As shown in FIG. 8, a pull-up circuit 3-1 used in the first embodimentof the level converter of the present invention is configured as below.That is, the configuration includes at least two (or two) p- MOS 1301 ofwhich respective source terminals are connected to a second power sourceterminal (VDDH), of which respective gate electrodes are connected to acontrol signal E1 from a third logic circuit 13, and of which respectivedrain terminals are connected respectively to level shift outputs (OUTH:out-high signal, OUTHB: out-high bar signal). By adopting the aboveconfiguration, the level shifter using the pull-up circuit in accordancewith the first embodiment of the present invention executes processingsimilar to that described above.

Each logic circuit of FIG. 4, particularly, the third logic circuit 13has a function to output control signals E0 and E1 according to controlof the first power source (VDDL). However, details thereof are notdirectly related to the present invention and hence description thereofwill be avoided. Incidentally, for the logic circuits such as the thirdlogic circuit 13 to output the control signals E0 and E1, knownconfigurations can be used.

Next, description will be given of an operation example of the firstembodiment. First, operation of the level shift core circuit 1 will bedescribed using the timing chart shown in FIG. 9. In the levelconverting operation using a differential power source level, levelshift inputs INL (IN low signal) and INLB (IN low bar signal) aredifferentially inputted at a first power source level, the output (OUTHor OUTHB) on the side connected to the n-MOS receiving a high-levelinput is reduced to Low, and an opposite-side output (OUTHB or OUTH) isincreased to a second power source level, i.e., High level.

On the other hand, the operation of the level converter including theswitching circuit 10 and the pull-up/pull-down circuit 3 is conductedaccording to the timing chart shown in FIG. 10. That is, when the firstpower source VDDL is in an on state, the control signals E0 and E1 fromthe third logic circuit 13 are High; when the switching circuit 10 is inan on state and the circuit 3 is in an off state, the level converterconducts a level converting operation similar to that of FIG. 9.

At transition of the first power source VDDL 12 to “off”, the controlsignals E0 and E1 are first changed to Low and the switching circuit 10is set to off such that the pull-up/pull-down circuit 3 is in an onstate, which prevents short circuit current of the level converter andwhich fixes the level shift outputs (OUTH,OUTHB) respectively to High.

As a result, even when the level shift inputs (INL,INLB) are indefinitewhen VDDL is set to off, the short circuit current and random outputchanges (random change-over between “on” and “off”) can be prevented.Next, to turn the first power source VDDL on, VDDL is first turned on toa stable state and then the control signals E0 and E1 are changed toHigh; the pull-up/pull-down circuit is turned off, the switching circuitis turned on; when one (OUTH) of the level shift outputs rises upaccording to a level shift input, the level converting operation isconducted in a way similar to that of FIG. 9.

As above, in the operation to control the first power source VDDL, sincethe switching circuit 10 is changed to off and the pull- up/pull-downcircuit 3 is changed to on, it is possible to prevent the short circuitcurrent and the random change of the output associated with theindefinite level shift input.

Therefore, even in an LSI having many power sources, reduction inleakage current can be achieved by turning the power source of an unusedblock off while suppressing the overhead as described above.

When only the level shift output OUTH is connected to the second logiccircuit 11 (e.g., only the output of OUTH or OUTHB is inputted as shownin FIGS. 11 and 13), the pull-up/pull-down circuit 3 used in theembodiment may be replaced by a circuit using only one p- MOS 101 asshown in FIG. 11. Additionally, when complementarity of the level shiftoutputs is required (two signal inputs of OUTH and OUTHB are requiredand these two signals are logically inverted), the circuit may bereplaced using one pull-up p-MOS 101301, one pull-down n-MOS 101302, anda control signal logic inverting inverter 101303 disposed in a precedingstage of the gate of n-MOS 101302 as shown in FIG. 12.

Furthermore, when the level shift output OUTH or OUTHB is required to beLow, the circuit may be replaced by a pull-down circuit including onen-MOS 101302 and an inverter 101303 to invert a control signal as shownin FIG. 13. When the pull-down circuit is adopted as a pull-up and/orpull-down circuit of the level converter of the present invention, if aninverted control signal is outputted from the third logic circuit side,the inverter 101303 of the pull-down circuit of FIG. 13 is not required.

As the level shift core circuit 1 used in the embodiment, one of thecircuits of FIGS. 14 to 19 may replace the level shift core circuit 1shown in FIG. 5 or 6. Incidentally, when the circuit shown in FIGS. 15,17, or 19 is used, the switching circuit 10 shown in FIG. 7 is connectedin parallel to outputs from n-MOS branched in two toward the GND side.In this situation, connection 1112 on the output side, i.e., theswitching circuit 10 to GND may be separately conducted or may beconducted in a shared way using one shared wiring line to GND.

Moreover, although the switching circuit is controlled using the controlsignal E0 of the third logic circuit in the embodiment, the controlsignal E1 may be adopted without using E0; or, inverted signals thereof(E0B, E1B) may also be used. Incidentally, in another embodiment,control signals E1 and E2 other than the control signal E0 and invertedsignals thereof (E0B, E1B, E2B) may also be employed appropriately.

In addition, although the switching circuit is controlled using thecontrol signal E0 from the third logic circuit 13 in the embodiment, thecontrol signal E1 may be adopted in place of E0. The replacement of thecontrol signal can also be used in embodiments described below;furthermore, in the following embodiments, E2 may be adopted in place ofE0 in the control operation.

Second Embodiment

The second embodiment of a level shifter in accordance with the presentinvention has a basic configuration similar to that of the firstembodiment as shown in FIG. 20. That is, like the first embodiment, thesecond embodiment includes a level shift core circuit 1, a pull-upand/or pull-down circuit 3, and a switching circuit 10. In theembodiment, the switching circuit 10 is disposed between the secondpower source (VDDH) and the power source terminal of the level shiftcore circuit 1, and the pull-up and/or pull-down circuit 3 may bereplaced only by a pull-down circuit (for example, FIG. 22 or 23). FIG.20 shows an overall configuration example of the level converter circuitas configured in the second embodiment. In the embodiment, unlike theconfiguration of the first embodiment in which the switching circuit isdisposed between the level converter and GND, the switching circuit isdisposed between VDDH and the level converter, and the level shift corecircuit receives INL and INLB outputted from the first logic circuit andoutputs OUTH or OUTHB to the second logic circuit.

FIG. 21 shows a configuration example of the switching circuit 10 usedin the level converter in accordance with the second embodiment shown inFIG. 20. The switching circuit 10 includes a p- MOS 11001 including adrain terminal connected to the power source terminal of the corecircuit 1, a gate electrode connected to an inverter output of thecontrol signal E0 from the third logic circuit 13, and a source terminal(reference is to be made to S of FIG. 21) connected to the second powersource VDDH.

Moreover, as shown in FIG. 22, the pull-down circuit 3-2 used in thelevel converter shown in FIG. 20 is configured as below. That is, thecircuit 3-2 includes two (at least two) n-MOS 301 including sourceterminals connected to the GND power source, gate terminals respectivelyconnected to an inverter output of the control signal E1 from the thirdlogic circuit 13, and drain terminals respectively connected to thelevel shift outputs (OUTH, OUTHB).

In the above configuration, the system executes processing similar tothat of the first embodiment described above.

When only the level shift output OUTH is connected to the second logiccircuit, the pull-down circuit 3-2 used in the embodiment may bereplaced by a circuit including an (only one) n-MOS 103-201 and aninverter as in the pull-down circuit shown in FIG. 23. As indicated bythe embodiment, there can be adopted a configuration in which one of thecontrol signals (OUTH or OUTHB) is fed to the second logic circuit.Furthermore, depending on cases, there may be used a configuration inwhich both signals (OUTH and OUTHB) are produced. Incidentally, althoughthe switching circuit is controlled using the control signal E0 from thethird logic circuit also in the third embodiment, the control operationcan be achieved using the control signal E1 in place of E0. Thissimilarly applies to embodiments described below. As above, themodification from the first embodiment to the second embodiment withrespect to the layout and the configuration of the switching circuit 10and the level shift core circuit 1 (the modification to dispose theswitching circuit 10 between the second power source (VDDH) and thelevel shift core circuit 1) can be adopted also in the third to theseventh embodiments, which will be described below. Incidentally, whenthe polarities of E0 and E1 are selected to be reversed, the inverter isnot required.

Third Embodiment

Description will be given of, as the third embodiment of a level shifterin accordance with the present invention, a level shifter capable ofimproving a level shift margin when a large potential difference existsbetween the first and second power sources. In the embodiment, controlhas been devised for the control circuit 2 to which the second powersource is supplied and the pull-up/pull-down circuit 3 to which thesecond power source (VDDH) is supplied. FIG. 24 shows a configurationexample of the embodiment. FIG. 24 includes a level shift input to whichthe second power source is supplied, a level shift output, a controlcircuit 2 which receives the control signal E2 from the third logiccircuit 13 and which outputs control signals (C0, C1, C2, C3) to apull-up/pull-down circuit 3, and the pull-up/pull-down circuit 3 whichis supplied with the second power source, which receives the controlsignals (C0, C1, C2, C3) from the control circuit 2 and the controlsignal E1 from the third logic circuit 13, and which connects an outputtherefrom to a level shift output.

As shown in FIG. 25, the control circuit 2 used in the level convertershown in FIG. 24 is configured as below. That is, the configurationincludes a first NAND circuit 103201 which is supplied with the secondpower source (VDDH) and which receives INL, OUTHB, and E2 as inputsthereto to output C0 therefrom, an NAND circuit 103202 which is suppliedwith the second power source and which receives INLB, OUTH, and E2 asinputs thereto to produce C1 therefrom, an inverter 103223 whichreceives C0 as an input thereto to output C3 therefrom, and an inverter103224 which receives C1 as an input thereto to produce C2 therefrom.

The short circuit current of the logic gate which is a problem when thelevel shift input (INL, INLB) of which the state changes depending onthe first power source to conduct power source control is indefinite issolved by disposing the NAND circuits 103201 and 103202 to receive thecontrol input E2 as an input thereto.

As shown in FIG. 26, an example of a pull-up/pull-down circuit 3(pull-up/pull-down circuit 3 capable of conducting 5-control-signal (C0-C3, E1) input and two-signal (OUTH and/or OUTHB) output operation) usedin the level converter shown in FIG. 24 is configured as below. That is,the circuit includes a p-MOS 103301 including a source terminalconnected to the second power source (VDDH), a gate terminal connectedto C0, and a drain terminal connected to OUTH; a p-MOS 103302 includinga source terminal connected to the second power source (VDDH), a gateterminal connected to C1, and a drain terminal connected to OUTHB; atleast two (two) p-MOS 103303 including source terminals respectivelyconnected to the second power source (VDDH), gate terminals connected toE1, and drain terminal connected to OUTH and OUTHB; an n-MOS 103304including a source terminal connected to the GND power source, a gateterminal connected to C2, and a drain terminal connected to OUTH; and ann-MOS 103305 including a source terminal connected to the GND powersource, a gate terminal connected to C3, and a drain terminal connectedto OUTHB.

Operation of the embodiment will be described. When E2 shown in thecontrol circuit 2 of FIG. 25 is set to low (Low), all of the MOStransistors (103301 and 103302 as well as 103304 and 103305) receivingC0 to C3 of FIG. 26 as inputs thereto are set to off (OFF); at thispoint of time, the two (at least two; plural) p-MOS 103303 of thepull-up/pull-down circuit 2 connected to E1 which is similarly set toLow turn on (ON) to pull up both of OUTH and OUTHB to high (High).

Moreover, as shown in FIG. 10, when the first power source VDDL is in anon state, the control signals E0 and E1 from the third logic circuit 13are High; in a case in which the switching circuit 10 is in an ON stateand the pull-up/pull-down circuit 3 is in an OFF state, when the levelshift input signals INL and INLB are differentially inputted at afirst-power-source level to the level shift core circuit 1, an operationis conducted in which the output (OUTH or OUTHB) from the side of thecore circuit 2 connected to an n-MOS to which high (High) is inputted isreduced to low (Low) and the other output is increased to a second powersource level, i.e., High. The operation of the level shift core circuitin this situation is similar to that of the level shift core circuitshown in FIG. 9.

To turn the first power source VDDL to off, the control signals E0 andE1 are first changed to Low, the switching circuit 10 is turned off, andthe pull-up/pull-down circuit 3 is set to an ON state to prevent theshort circuit current of the level converter on one hand and to fix thelevel shift outputs (OUTH, OUTHB) respectively to High on the other.

As a result, even when conversion outputs (OUTH, OUTHB) are indefinitewhen VDDL is turned off, the short circuit current and the randomchanges in the output (random change-over between on and off) can beprevented. Next, to turn the first power source VDDL on, VDDL is firstturned on to be stabilized, the control signals E0 and E1 are thenchanged to High, the pull-up/pull-down circuit is turned off (OFF), theswitching circuit is turned on (ON); after one (OUTH) of the level shiftoutputs rises up according to the level shift input, the level shift isconducted in a way similar to that of FIG. 9 described above.

As above, to control the first power source VDDL, the switching circuit10 is set to OFF and the pull-up/pull-down circuit 3 is set to ON, andhence the short circuit current and the random changes in the outputassociated with the indefinite level shift input can be prevented.

Therefore, even in an LSI having many power sources, the leakage currentcaused by turning off a power source of an unused block can be reducedwhile the overhead is suppressed as described above.

FIG. 27 shows a configuration example of the NAND circuits 103201 and103202 shown in FIG. 25, the NAND circuits constituting the controlcircuit 2 used in the level converter of the present invention describedabove. In FIG. 27, the control signal E2 is connected to an n-MOS103001-6 (or 103002-6) most apart from the output terminal. Thisconnection is possible because the E2 signal has a weak restriction withrespect to delay. Contrarily, the level shift input (INL, INLB) has astrong restriction with respect to delay and is connected to an n- MOS103001-4 (or 103002-4) near the output terminal. This is because thegate delay can be reduced as compared with a case in which the input isconnected to an n-MOS apart from the output terminal. However, the levelshift input is at a first power source level; when the potentialdifference with respect to the second power source becomes large or whenthe threshold value of the n-MOS is large, particularly, when theinfluence of increase in the n-MOS threshold value due to a substrateeffect becomes strong, the delay becomes increased when the input isconnected to an n-MOS near the output terminal depending on cases. Inthis case, the delay elongation can be prevented by connecting the inputto an n-MOS which is apart from the output terminal and which is lessinfluenced by the substrate effect. It is not necessarily required tofollow the input order of FIG. 27. Moreover, a p-MOS connected to thelevel shift input does not turn off depending on the p-MOS thresholdvalue since the high level of the level shift input is less than that ofthe second power source, and the n-MOS does not fully turn on and hencethere exists a chance in which the NAND operation is difficult. In thiscase, the NAND operation can be guaranteed by reducing a ratio of p-MOSchannel width/length (W/L), by reducing the threshold value (byincreasing the absolute value when the polarity is negative), byincreasing W/L of the associated n-MOS, or by changing the thresholdvalue by reducing the absolute value when the polarity is positive.Additionally, even when the logic operation is possible, the NANDleakage can be suppressed by reducing W/L of the p-MOS or by reducingthe threshold value (e.g., by setting the threshold value to VDDL-VDDHor less, that is, by increasing the absolute value when the polarity isnegative).

FIG. 28 shows a timing chart of the operation of the level converter.When the first power source (VDDL) is on and the control signals (E0,E1, E2) from the third logic circuit 13 are High, the level shiftoutputs (OUTHB, OUTH) are obtained according to changes in the levelshift inputs (INL, INLB). Particularly, the control circuit 2 controlsthe pull-up/pull-down circuit 3 to enhance the state change.

In a case in which the first power source (VDDL) is turned off, E0 isbeforehand set to Low to turn the switching circuit 10 off and E1 is setto Low to fix the level shift output (either one of OUTH and OUTHB) toHigh, and then the first power source (VDDL) is turned off.

To turn the first power source (VDDL) on, the first power source isfirst turned on; after the power source is stabilized, the controlsignals are controlled.

When the level converter and the second logic circuit 11 are onlyconnected (input) to OUTH, the pull-up and/or pull-down circuit 3 usedin the embodiment may be replaced with the pull-up/pull-down circuit 3shown in FIG. 29. When the converter and the circuit 11 are onlyconnected (input) to OUTHB, the drain terminal of the p-MOS including agate terminal connected to the control signal E1 is connected to OUTHB,not OUTH.

Furthermore, in the pull-up and/or pull-down circuit 3 used in theembodiment, when it is required to fix OUTH to High and OUTHB to Low,the circuit 3 may be replaced with the pull-up and/or pull-down circuit3 shown in FIG. 30 or 31. In this case, however, it is required thateither one of the level shift inputs INL and INLB is guaranteed to beLow when the first power source VDDL is controlled and hence occurrenceof the short circuit current is prevented.

In the embodiment, to include only a pull-up circuit 3-1 at level shift,the control circuit 2 and the pull-up and/or pull-down circuit 3 may berespectively replaced by FIG. 32 and FIGS. 33 to 36 (a pull-up and/orpull-down circuit 3 capable of achieving 3-control-signal (two controlsignals selected from C0 to C3, such as C0 and C1 or C2 and C3, and theE1 signal) input, two-signal (OUTH and/or OUTHB) output). Restrictionson the replacement by FIGS. 33 to 36 are similar to those of the case ofFIG. 26 and FIGS. 29 to 31. This is not the case if the level shift corecircuit 1 shown in FIG. 6, 15, 17, 19, or 37 described above is used andthe n-MOS and the n-MOS of the switching circuit are respectively andindependently connected in parallel.

To operate only the pull-down (3-2) function at level shift, the controlcircuit 2 and the pull-up and/or pull-down circuit 3 used in theembodiment may be respectively replaced by FIG. 38 and FIGS. 39 to 42.

Restrictions on the replacement by FIGS. 39 to 42 are similar to thoseof the case of FIG. 26 and FIGS. 29 to 31.

Moreover, the control circuit adopted in the embodiment may berespectively replaced by FIGS. 43 to 45. Functions and operations afterthe replacement by FIGS. 43 to 45 are similar respectively to those ofFIGS. 25, 32, and 38, and hence description thereof will be avoided.

In conjunction with FIGS. 43 to 45, FIG. 46 shows an example of NORcircuits shown in FIGS. 43 to 45. In FIG. 46, a control signal E2B (aninverted signal of E2) is connected to a p-MOS 102601 most apart from anoutput terminal. This is because E2B has a weakest restriction withrespect to delay. Furthermore, by connecting the level shift input (INL,INLB) to a p-MOS near the output terminal, the gate delay thereof can bereduced as compared with the case in which the input is connected to ap-MOS apart from the output terminal. However, it is not necessarilyrequired to follow the input order of FIG. 46. In addition, for thep-MOS connected to the level shift input, the High level of the levelshift input cannot reach the second power source voltage level, andhence the p-MOS does not turn on depending on its threshold value;moreover, the n-MOS does not fully turn on, and hence the NOR operationis difficult in some cases. In this situation, as described above, theNOR operation can be guaranteed by reducing a ratio of p-MOS channelwidth/length (W/L), by reducing the threshold value (VDDL-VDDH or less;by increasing the absolute value when the polarity is negative), byincreasing W/L of the associated n-MOS, or by reducing the thresholdvalue. Furthermore, even when the logic operation is possible, the NORleakage can be suppressed by minimizing the W/L of the p-MOS or byreducing the threshold value (by setting the threshold value toVDDL-VDDH or less. That is, by setting the polarity to negative and byincreasing the absolute value as described above).

Incidentally, in the description of the embodiment, the control signalsE0 to E2 outputted from the third logic circuit are used in this casesuch that the pull-up and/or pull-down circuit uses E1, the controlcircuit utilizes E2, and the switching circuit 10 employs E0 forcontrol. However, the control signals E0 to E2 inputted to the pull-upand/or pull-down circuit, the control circuit, and the switching circuit10 may be respectively replaced by other control signals according toneed. Additionally, the level shifter may also be configured by usingeither one of the OUTH signal and the OUTHB signal and by exchanging thelayout of the level shift circuit 1 and the switching circuit in anexample of change from the first embodiment 1 to the second embodiment.

Fourth Embodiment

The fourth embodiment of the present invention is implemented bydevising the control circuit 2 such that the control signal E1 isremoved from the third logic circuit 13 and the pull-up and/or pull-down circuit 3 is simplified, adopting other fundamental configurationssimilar to one of the embodiments described above. FIG. 47 shows theconfiguration.

FIG. 48 shows the control circuit 2 used in the level converter shown inFIG. 47. As shown in FIG. 48, the control circuit 2 used in theembodiment is configured as below. That is, when compared with FIG. 25,the NAND circuit to output C0 is replaced by an AND-NOR circuit and aninverted signal (E2B) of E2 is inputted to a NOR section of the AND-NORcircuit. As a result, when E2 becomes Low, C0 is set to High, and C3 isset to Low. Excepting the change in the signal functions, the embodimentoperates in a way similar to that of the third embodiment describedabove.

FIG. 49 shows the pull-up/pull-down circuit 3 used in the levelconverter shown in FIG. 47. The configuration of the circuit will benext described. That is, as compared with FIG. 30, the p-MOS 103322including a gate terminal to which E1 is inputted, the inverter 103326,and the n-MOS 103325 including a gate terminal connected to an outputfrom the inverter can be removed. However, like in FIG. 30, this appliesonly to a case in which either one of the level shift inputs INL andINLB is guaranteed to be at Low when the first power source VDDL iscontrolled and the occurrence of the short circuit current is prevented.

The AND-NOR circuit of FIG. 48 is configured, for example, as shown inthe diagram, as below. That is, a p-MOS 102 including a gate terminalconnected to the inverted signal E2B of the control signal E2 isdisposed on the power source side. This is because E2B has a weakrestriction with respect to delay. The other configurations are similarto those of the NAND circuit of FIG. 27. In FIG. 50, INL or INLB andOUTH or OUTHB are respective inputs to two n-MOS; this indicates thatthe input signal is a combination of INL and OUTH, INL and OUTHB, INLBand OUTH, or INLB and OUTHB. When INL or INLB and OUTH or OUTHB areused, the input signals are indicated as the combinations as above inthis specification.

The timing chart of FIG. 51 shows an operation example of the levelshifter shown in FIG. 47.

The control circuit 2 and the pull-up/pull-down circuit 3 used in theembodiment may be replaced by the circuits respectively shown in FIGS.52 and 53 in a case in which only OUTH of the level shift outputs isfixed to a High level when the first power source is off to achieve onlythe pull-up (3-1) function at level shift. The control circuit 2 and thepull-up/pull-down circuit 1 (reference is to be made to FIG. 53) used inthe embodiment may be replaced by the circuit configurationsrespectively shown in FIGS. 54 and 55 in a case in which only the pull-up (3-1) function is used at level shift and OUTH of the level shiftoutputs is fixed to High and OUTHB is fixed to Low when the first powersource is off. Additionally, the control circuit 2 used in theembodiment may be replaced by any one of FIGS. 56 to 58. The levelshifter thus replaced operates in a way similar to that described in theparagraphs of FIGS. 48, 52, and 54 and achieves a function similar tothat of the circuit before the replacement.

The OR-NOR circuit used in FIGS. 56 to 58 is configured, for example, asshown in the diagrams, as below. That is, an n-MOS including a gateterminal connected to the control signal E2 is disposed on the GND powersource side. This is because E2 has a weak restriction with respect todelay. The other configurations are similar to those of the NOR circuitof FIG. 46.

The control circuit 2 used in the embodiment may be replaced by anyeither one of FIGS. 60 and 61 in a case in which OUTH and OUTHB of thelevel shift outputs are fixed to High when the first power source is offto enable operation of only the pull-up (3-1) function or the pull- down(3-2) function or in a case in which OUTH and OUTHB are fixed to Low forthe pull-down (3-2). However, this applies only to a case in which theshort circuit current is absent when the switching circuit is disposedat a position on the power source side.

Fifth Embodiment

The fifth embodiment of the present invention has devised control in aconfiguration of a level shifter capable of improving the level shiftmargin when a large potential difference exists between the first andsecond power sources, the circuit including a control circuit 2 to whichthe second power source is supplied and a pull-up/pull-down circuit 3 towhich the second power source is supplied. In this embodiment, controlof a level shift core circuit 1 is particularly devised. FIG. 64 shows aconfiguration thereof. In FIG. 64, as compared with FIG. 24, the controlcircuit 2 prepares control signals C4 and C5 to control the core circuit1.

The level shift core circuit adopted in the level converter of FIG. 64is configured, as shown in FIG. 65, as below. That is, when theembodiment adopts FIG. 18 or 19 showing a configuration example of thelevel shift core circuit 10, the configuration is modified such that thecontrol signals C4 and C5 from the control circuit 2 control gateterminals of two p-MOS switches including drain terminals connected tooutputs.

In addition, FIG. 66 shows another embodiment of the level shifter. Thecontrol circuit 2 used in FIG. 66 is configured, as shown in FIG. 64, asbelow. That is, as compared with the circuit shown in FIG. 25, theconfiguration produces C4 and C5 in addition to C3 and C2. For theconfiguration of the pull-up/pull-down circuit 3 which can be used inthe embodiment, there can be employed, for example, FIG. 26;furthermore, in place of the pull-up/pull-down circuit, thepull-up/pull- down circuit shown in one of FIGS. 29 to 31 can beadopted. Operation thereof is similar to that of the cases describedabove.

The control circuit 2 used in the embodiment may also be replaced by, inplace of the control circuit 2 shown in FIG. 66, the circuit shown inFIG. 67. Also, to achieve only the pull-up function at level shift, thecontrol circuit 2 can be replaced by, in place of the control circuitshown in FIG. 66, the circuit configuration shown in FIG. 68 or 69.Furthermore, to achieve only the pull-down 3-2 function at level shift,the control circuit 2 can be replaced by, in place of the controlcircuit shown in FIG. 66, the circuit configuration shown in FIG. 70 or71. Additionally, when neither the pull-up function nor the pull-down3-2 function is employed, the control circuit 2 can be replaced by, inplace of the control circuit shown in FIG. 66, the circuit configurationshown in FIG. 72 or 73. To achieve the pull-up function when thesecontrol circuits are adopted, it is possible to utilize FIGS. 33 and 34or FIGS. 35 and 36 (also including the pull-down function). In thisregard, although these pull-up and/or pull-down circuits receive thecontrol signals C0 and C1 as inputs thereto, when the signals arereplaced by C2 and C3, any one of the pull-up and/or pull-down circuitsof FIGS. 39 to 42 can be used. Besides, operations of the controlcircuit 2 and the pull-up and/or pull-down circuit 3 are similar tothose of the embodiments described above; the level shifter may also beconfigured (modified) including any combination other than those aboveof the control circuit and the pull-up and/or pull-down circuit, whichis also included in the present invention. In short, according to theembodiment, excepting the restriction to produce the control signals C4and C5, no restriction exists for the other control signals to beproduced, and the control signals can be freely selected; in a case inwhich the C0 to C5 signals (C0 to C3 signals as the other controlsignals) are selected as such other control signals like in FIG. 66 asshown in, for example, FIG. 67, there can be considered an example ofthe control circuit in which an NOR circuit is adopted in place of theNAND circuit of FIG. 66. Moreover, FIG. 68 shows an example of thecontrol circuit which selects the C0 and C1 signals as the other controlsignals to select the NAND circuit. Like FIG. 68, FIG. 69 shows anexample of the control circuit which selects the C0 and C1 signals asthe other control signals to select the NOR circuit. Next, FIG. 70 showsan example of the control circuit which selects the C2 and C3 signals asthe other control signals to select the NAND circuit, and FIG. 71 showsan example of the control circuit which selects the C2 and C3 signals asthe other control signals to select the NOR circuit. Additionally, FIG.72 shows an example of the control circuit including a NAND circuitconfiguration which does not produce the other control signals and whichproduces only the C4 and C5 signals as the control signals; FIG. 73shows the control circuit including a NOR configuration.

In an operation example of the fifth embodiment described above, in acase in which INL is Low, INLB is High, OUTH is Low, and OUTHB is High,when the INL signal produced from the first logic circuit becomes High(INLB is Low), the control circuit 2 receives the INL signal as an inputthereto and then produces a C0 signal and the like. The C0 signal thusproduced is Low and then the p-MOS in the pull-up and/or pull-downcircuit 3 connected to OUTH turns on to pull up OUTH; at the same time,the control circuit 2 produces C3 of High. As a result, the n-MOSconnected to OUTHB in the pull-up and/or pull-down circuit 3 turns on topull down OUTHB; the control circuit 2 produces C4 of High to turn ap-MOS switch in the pull-up and/or pull- down circuit 3 connected toOUTHB off to suppress the pull-up of OUTHB; at the same time, when OUTHBis reduced to Low by an operation of the level shift core circuit 1, thecontrol circuit 2 produces C0 of High to turn the n-MOS in the pull-upand/or pull-down circuit 3 to finish the pull-up, and the controlcircuit p2 produces C3 of Low to turn the n-MOS in the pull-up and/orpull-down circuit 3 off to finish the pull-down; the control circuit 2produces C4 of Low to turn the p- MOS switch in the pull-up and/orpull-down circuit 3 on. Resultantly, INL is High, INLB is Low, OUTH isHigh, and OUTHB is Low.

Next, when an external first logic circuit 4 sets INLB to High (INL isLow), this signal is fed to the controller 2 and the controller 2produces C1 of Low to turn on the p-MOS in the pull-up and/or pull- downcircuit 3 connected to OUTHB to pull up OUTHB; moreover, the controller2 produces C2 of High to turn on the n-MOS in the pull-up and/orpull-down circuit 3 connected to OUTH to pull down OUTH; the controller2 produces C5 of High to turn on the p-MOS in the pull-up and/orpull-down circuit 3 connected to OUTH to suppress the pull-up of OUTH;at the same time, when OUTH is reduced to Low by an operation of thelevel shift core circuit 1, the- control circuit 2 produces C1 of Highto turn the p-MOS in the pull-up and/or pull-down circuit 3 off tofinish the pull-up; furthermore, the control circuit 2 produces C2 ofLow to turn the n-MOS in the pull-up and/or pull-down circuit 3 off tofinish the pull-down; the control circuit 2 produces C5 of Low to turnthe p-MOS switch in the pull-up and/or pull-down circuit 3 on. As aresult, INL is Low, INLB is High, OUTH is Low, and OUTHB is High. Inthis connection, description has been given of a case in which theconfiguration shown in FIG. 7 described above is adopted for the n-MOS(transistor) and the p-MOS (transistor) of the pull-up and/or pull-downcircuit 3. However, in a case in which the n-MOS is replaced by thep-MOS and/or the p-MOS is replaced by the n-MOS, the operation isconducted by changing the connection between the OUTH signal and theOUTHB signal and by interpreting also the description of the operationaccording to the change.

Sixth Embodiment

In the sixth embodiment of the present invention, the idea or the deviceof FIG. 47 is applied to FIG. 64. FIG. 74 shows a configurationconcretely representing the idea. In this diagram, the control circuit 2shown in FIG. 75 is devised as below. That is, the embodiment does notrequire E1 controlling the pull-up/pull-down circuit 3 and simplifiesthe pull-up/pull-down circuit 3.

As shown in FIG. 75, the control circuit 2 used in the level shifteraccording to FIG. 74 is configured as below. That is, as compared withFIG. 48, there are produced C4 and C5 in addition to C3 and C2. As thepull-up/pull-down circuit 3 adopted in FIG. 74 may be similar to thatused in the level converter circuit of the fourth embodiment shown inFIG. 47.

The control circuit 2 shown in FIG. 75 and used in the embodiment may bereplaced by the control circuit 2 shown in FIG. 76. Furthermore, whenonly the pull-up (3-1) function is achieved at level shift, the controlcircuit 2 can be replaced with FIG. 77 or 78; additionally, when onlythe pull-down (3-2) function is achieved at level shift, the controlcircuit 2 can be replaced with FIG. 79 or 80; also, when neither thepull-up function nor the pull-down function is used at level shift, thecontrol circuit 2 can be replaced with FIG. 81 or 82.

Operation of the embodiment is similar to that of the operation of theembodiments described above.

Seventh Embodiment

As shown in FIGS. 83 and 84, in the seventh embodiment of the presentinvention, the control circuit 2 is devised as compared with FIGS. 64and 74. FIGS. 79 and 80 show configurations thereof. In these diagrams,when the pull-up/pull-down circuit 3 achieves only the pull-down (3-2)function, the switching circuit is not required. As an example of thecontrol circuit, a circuit similar to that of FIG. 79 or 80 may be used;as shown in FIG. 85, a timing example of the level shifter of FIG. 85 isrepresented as below.

That is, when E2 is Low, C4 and C5 are at a High level, and the p-MOS ofthe level shift core circuit 1 including a gate terminal connectedthereto functions as a switch disposed on the power source side to turnthese signals off. Through this operation, resultantly, the power sourceGND short circuit current path can be prevented regardless of the levelshift input.

Moreover, in the embodiment described above, it is assumed that thecontrol signal outputs (E0, E1, E2) from the third logic circuit 13 areset to Low when the first power source is turned off; however, thecontrol circuit and the pull-up/pull-down circuit 3 can also berespectively simplified by appropriately using inverted signals. In thediagrams used to described the embodiments, p-MOS (transistor) has acircle (□) on the gate section. Incidentally, the present invention isnot restricted by the embodiments, and the embodiments can beappropriately modified within a scope of the technical idea of thepresent invention, and those modified embodiments are also included inthe invention of this application. Additionally, E0, E1, and E2 can becollectively used as one signal when they have common timing. Moreover,in the timing charts of FIGS. 10, 28, etc., the section indicated by Xrepresents an indefinite state.

INDUSTRIAL APPLICABILITY

As described above, in accordance with the present invention, shortcircuit current and the delay increase can be suppressed on the basis ofa fundamental configuration of a level shifter for converting a signallevel of a first logic circuit to which a first power source is suppliedinto a signal level of a second logic circuit to which a second powersource is supplied, characterized by including a switching circuitbetween a GND power source terminal (ground power source terminal) of alevel shift core circuit and a GND power source (ground power source),the switching circuit being controlled by a third logic circuit whichgenerates a control signal under control of the first power source, anda pull-up and/or pull-down circuit at an output of the level shift corecircuit, the pull-up and/or pull-down circuit being controlled by thethird logic circuit. In this connection, as the basic configurations ofthe level shift core circuit 1, the switching circuit 10, the controlcircuit 2, and the pull-up and/or pull-down circuit 3, those describedabove can be adopted; however, these may be used such that two or morecircuits are connected in parallel in a circuit configuration; forexample, it is also possible that two or more level shift core circuitsor the like are connected in parallel to be utilized as a level shiftcore circuit.

1. A level converting circuit for converting a signal level of a firstlogic circuit to which a first power source is supplied into a signallevel of a second logic circuit to which a second power source issupplied, characterized by including a pull-up and/or pull-down circuitin which the second power source is supplied to a level conversionoutput of a level conversion core circuit and a switching circuitbetween a GND power source terminal (ground power source terminal) ofthe level conversion core circuit and a GND power source (ground powersource), the switching circuit being controlled by a third logic circuitto produce a control signal under control of the first power source, thethird logic circuit producing control signals to control the pull-upand/or pull-down circuit and the switching circuit, the level conversioncore circuit including a p-MOS cross-coupled latch including at leasttwo first p-MOS, a differential n-MOS including at least two n-MOS, andat least two second p- MOS, the p-MOS cross-coupled latch including asource terminal connected to the second power source and a gate terminalconnected to a level conversion output which is each drain terminal of asecond pMOS, the differential n-MOS including each source terminalconnected to the GND power source, each drain terminal connected to thelevel conversion output, and each gate terminal connected to a levelconversion input, the second p-MOS including each source terminalconnected of the first p-MOS, each gate terminal connected to the levelconversion input, and each drain terminal connected to the levelconversion output.
 2. A level converting circuit for converting a signallevel of a first logic circuit to which a first power source is suppliedinto a signal level of a second logic circuit to which a second powersource is supplied, characterized by including a switching circuitbetween a power source terminal of a level conversion core circuit andthe second power source, the switching circuit being controlled by athird logic circuit which generates a control signal under control ofthe first power source, and a pull-up and/or pull-down circuit at anoutput of the level conversion core circuit, the pull-up and/orpull-down circuit being controlled by the third logic circuit, the thirdlogic circuit producing control signals to control the pull-up and/orpull-down circuit and the level conversion core circuit.
 3. A levelconverting circuit in accordance with claim 1 or 2, characterized inthat: the level conversion core circuit includes a p-MOS cross-coupledlatch including at least two p-MOS and a differential n-MOS including atleast two n-MOS; each of the p-MOS includes a source terminal connectedto the second power source terminal and a gate terminal connected to alevel conversion output which is each drain terminal; and each of then-MOS includes a source terminal connected to the cross-coupled latchand the GND power source terminal, a drain terminal connected to thelevel conversion output, and a gate terminal connected to a levelconversion input.
 4. (canceled)
 5. A level converting circuit forconverting a signal level of a first logic circuit to which a firstpower source is supplied into a signal level of a second logic circuitto which a second power source is supplied, characterized by including apull-up and/or pull-down circuit in which the second power source issupplied to a level conversion output of a level conversion core circuitand a switching circuit which is disposed between a power sourceterminal of the level conversion core circuit and the second powersource and which is controlled by a third logic circuit, the third logiccircuit generating a control signal under control of a first powersource, wherein the control circuit is controlled by a control signalfrom the third logic circuit.
 6. A level converting circuit forconverting a signal level of a first logic circuit to which a firstpower source is supplied into a signal level of a second logic circuitto which a second power source is supplied, characterized by including apull-up and/or pull-down circuit in which the second power source issupplied to a level conversion output of a level conversion corecircuit, a control circuit to which the second power source is suppliedand which receives as inputs thereto a level conversion input signal andthe level conversion output signal, and a switching circuit which isdisposed between a power source terminal of the level conversion corecircuit and the second power source and which is controlled by a third‘logic circuit, the third to circuit generating a control signal undercontrol of the first power source, wherein the control circuit iscontrolled by a control signal from the third ‘logic circuit.
 7. A levelconverting circuit, characterized in that the third logic circuitcontrols the control circuit by a control signal from the third logiccircuit, and the control circuit produces control signals to control thepull-up and/or pull-down circuit and the level conversion core circuit.8. A level converting circuit in accordance with claim
 7. characterizedin that the control circuit further produces a control signal to controlthe pull-up and/or pull-down circuit to thereby control the pull- upand/or pull-down circuit.
 9. (canceled)
 10. A level converting circuitin accordance with claim 8, characterized in that the pull-up and/orpull-down circuit comprises a p-MOS including a source terminalconnected to the second power source, a gate terminal connected to acontrol signal, and a drain terminal connected to one of the levelconversion outputs and an n-MOS including a source terminal connected toa GND power source, a gate terminal connected to an inverted signal of acontrol signal, and a drain terminal connected to other one of the levelconversion outputs.
 11. A level converting circuit in accordance withclaim 7, characterized in that the pull-up and/or pull-down circuitincludes at least two p-MOS each of which includes a source terminalconnected to the second power source and a gate terminal connected to acontrol signal from the control circuit, each drain terminal of otherpMOS being connected to each of the level conversion outputs; at leasttwo n-MOS each of which includes a source terminal connected to the GNDpower source, a gate terminal connected to a control signal from thecontrol circuit, and a drain terminal connected to the level conversionoutputs, and additionally at least two p-MOS each of which includes asource terminal connected to the second power source and a gate terminalconnected to a control signal from the third logic circuit, a drainterminal of other p-MOS being connected to each of the level conversionoutputs.
 12. A level converting circuit in accordance with claim 7,characterized in that the pull-up and/or pull-down circuit includes atleast two p-MOS each of which includes a source terminal connected tothe second power source and a gate terminal connected to a controlsignal from the control circuit, each drain terminal of other p MOSbeing connected to each of the level conversion outputs; at least twon-MOS each of which includes a source terminal connected to the GNDpower source, a gate terminal connected to a control signal from thecontrol circuit, and a drain terminal connected to the level conversionoutputs; and additionally a p-MOS including a source terminal connectedto the second power source, a gate terminal connected to a controlsignal from the third logic circuit, a drain terminal connected to oneof the level conversion outputs.
 13. A level converting circuit inaccordance with claim 7, characterized in that the pull-up and/orpull-down circuit includes at least two p-MOS each of which includes asource terminal connected to the second power source, a gate terminalconnected to a control signal from the control circuit, and a drainterminal connected to each of the level conversion outputs, at least twon-MOS each of which includes a source terminal connected to the GNDpower source, a gate terminal connected to a control signal from thecontrol circuit, and a drain terminal connected to the level conversionoutputs: additionally a p- MO including a source terminal connected tothe second power source, a gate terminal connected to a control signalfrom the third logic circuit, and a drain terminal connected to one ofthe level conversion outputs; and additionally an n-M-ZOS including asource terminal connected to the GND power source, a gate terminalconnected to a control signal from the third logic circuit or to aninverted signal of the control signal, and a drain terminal connected toother one of the level conversion outputs.
 14. A level convertingcircuit in accordance with claim 7, characterized in that the pull-upand/or pull-down circuit includes at least two p-MOS each of whichincludes a source terminal connected to the second power source and agate terminal connected to a control signal from the control circuit, adrain terminal of other pMOS being connected to each of the levelconversion outputs; at least two n-MOS each of which includes a sourceterminal connected to the GND power source, a gate terminal connected toa control signal from the control circuit, and a drain terminalconnected to the level conversion outputs; and additionally an n-MOSincluding a source terminal connected to the GND power source, a gateterminal connected to a control signal from the third logic circuit orto an inverted signal of the control signal, and a drain terminalconnected to one of the level conversion outputs.
 15. A level convertingcircuit in accordance with claim 7, characterized in that the controlcircuit comprises a NAND circuit to which the second power source issupplied and which receives as inputs thereto a positively invertedsignal of the level conversion input signal, an inverted signal of thelevel conversion output signal, a positively inverted signal of thelevel conversion output signal, and a control output of the third logiccircuit, wherein an output signal of the NAND circuit is produced tocontrol a signal.
 16. A level converting circuit in accordance withclaim 15, characterized in that the NAND circuit is of a CMOS circuitconfiguration and the p-MOS transistor to which the level conversioninput signal is connected includes a transistor at least having a smallratio of a channel width/a channel length or a high threshold value. 17.A level converting circuit in accordance with claim 15, characterized inthat the NAND circuit is of a CMOS circuit configuration and the n-MOStransistor to which a control signal output of the third logic circuitis connected includes a source terminal connected to a GND power source.18. (canceled)
 19. A level converting circuit in accordance with claim15, characterized in that the pull-up and/or pull-down circuit furtherincludes at least two p-MOS each of which includes a source terminalconnected to the second power source and a gate terminal connected to acontrol signal from the control circuit, a drain terminal of other pMOSbeing connected to each of the level conversion outputs; andadditionally at least two p-MOS each of which includes a source terminalconnected to the second power source and a gate terminal connected to acontrol signal from the third logic circuit, a drain terminal of otherp-MOS being connected to each of the level conversion outputs.
 20. Alevel converting circuit in accordance with claim 15, characterized inthat the pull-up and/or pull-down circuit further includes at least twop-MOS each of which includes a source terminal connected to the secondpower source, a gate terminal connected to a control signal from thecontrol circuit, and a drain terminal connected to each of the levelconversion outputs; and additionally a p-MOS including a source terminalconnected to the second power source, a gate terminal connected to acontrol signal from the third logic circuit, and a drain terminalconnected to one of the level conversion outputs.
 21. A level convertingcircuit in accordance with claim 15, characterized in that the pull-upand/or pull-down circuit includes at least two p-NIOS each of whichincludes a source terminal connected to the second power source, a gateterminal connected to a control signal from the control circuit, and adrain terminal connected to each of the level conversion outputs:additionally a p-MOS including a source terminal connected to the secondpower source, a gate terminal connected to a control signal from thethird logic circuit, and a drain terminal connected to one of the levelconversion outputs; and additionally an n-MOS including a sourceterminal connected to the GND power source, a gate terminal connected toa control signal from the third logic circuit or to an inverted signalof the control signal, and a drain terminal connected to other one ofthe level conversion outputs.
 22. A level shifter in accordance withclaim 18, characterized in that the pull- up and/or pull-down circuitincludes at least two p-MOSs each of which includes a source terminalconnected to the second power source, a gate terminal connected to acontrol signal from the control circuit, and a drain terminal connectedto each of the level shift outputs; and additionally an n-MOS includinga source terminal connected to the GND power source, a gate terminalconnected to a control signal from the third logic circuit or aninverted signal of the control signal, and a drain terminal connected toone of the level shift outputs.
 23. A level shifter in accordance withclaim 7, characterized in that the control circuit comprises a NANDcircuit to which the second power source is supplied and which receivesas inputs thereto a positively inverted signal of the level shift inputsignal, an inverted signal of the level shift output signal, and acontrol output of the third logic circuit, a NAND circuit to which thesecond power source is supplied and which receives as inputs thereto aninverted signal of the level shift input signal, a positively invertedsignal of the level shift output, and a control output of the thirdlogic circuit, and at least two inverters to which the second powersource is supplied and which respectively receive as inputs theretooutputs from the NAND circuits, wherein each output signal from theinverters is produced as a control signal.
 24. A level shifter inaccordance with claim 18, characterized in that the pull-up and/orpull-down circuit includes at least two n-MOSs each of which includes asource terminal connected to the GND power source, a gate terminalconnected to a control signal from the control circuit, and a drainterminal connected to the level shift outputs and additionally at leasttwo p-MOSs each of which includes a source terminal connected to thesecond power source and a gate terminal connected to a control signalfrom the third logic circuit, a drain terminal of other p-MOS beingconnected to each of the level shift outputs.
 25. A level shifter inaccordance with claim 23, characterized in that the pull- up and/orpull-down circuit includes at least two n-MOS each of which includes asource terminal connected to the GND power source, a gate terminalconnected to a control signal from the control circuit, and a drainterminal connected to the level shift outputs and additionally a p- MOSincluding a source terminal connected to the second power source, a gateterminal connected to a control signal from the third logic circuit, anda drain terminal connected to one of the level shift outputs.
 26. Alevel shifter in accordance with claim 23, characterized in that thepull- up and/or pull-down circuit includes at least two n-MOSs each ofwhich includes a source terminal connected to the GND power source, agate terminal connected to a control signal from the control circuit,and a drain terminal connected to the level shift output; additionally ap-MOS including a source terminal connected to the second power source,a gate terminal connected to a control signal from the third logiccircuit, and a drain terminal connected to one of the level shiftoutputs; and additionally an n-MOS including a source terminal connectedto the GND power source, a gate terminal connected to a control signalfrom the third logic circuit or an inverted signal of the controlsignal, and a drain terminal connected to other one of the level shiftoutputs.
 27. A level shifter in accordance with claim 23, characterizedin that the pull- up and/or pull-down circuit includes at least twon-MOSs each of which includes a source terminal connected to the GNDpower source, a gate terminal connected to a control signal from thecontrol circuit, and a drain terminal connected to the level shiftoutputs and additionally an n- MOS including a source terminal connectedto the GND power source, a gate terminal connected to a control signalfrom the third logic circuit or to an inverted signal of the controlsignal, and a drain terminal connected to other one of the level shiftoutputs.
 28. A level shifter in accordance with one of claims 14 to 17,characterized in that the control circuit comprises a NOR circuit towhich the second power source is supplied and which receives as inputsthereto an inverted signal of the level shift input signal, a positivelyinverted signal of the level shift output signal, and a control outputof the third logic circuit or an inverted signal of the control output,a NOR circuit to which the second power source is supplied and whichreceives as inputs thereto a positively inverted signal of the levelshift input signal, an inverted signal of the level shift output, and acontrol output of the third logic circuit or an inverted signal of thecontrol output, and at least two inverters to which the second powersource is supplied and which respectively receive as inputs theretooutputs from the NOR circuits, wherein output signals respectively fromthe at least two NOR circuits and the at least two inverters areproduced as control signals.
 29. A level shifter in accordance withclaim 28, characterized in that the NOR circuits are of a CMOS circuitconfiguration and a p-MOS to which the level shift input signal isconnected includes a transistor at least having a small ratio of achannel width/a channel length or a threshold value which is of anegative polarity and which is a large absolute value.
 30. A levelshifter in accordance with claim 28, characterized in that the NORcircuits are of a CMOS circuit configuration and a control signal fromthe third logic circuit or an inverted signal thereof is connected to ap-MOS on a power source side.
 31. A level shifter in accordance with oneof claims 19 to 22, characterized in that the control circuit comprisesa NOR circuit to which the second power source is supplied and whichreceives as inputs thereto an inverted signal of the level shift inputsignal, a positively inverted signal of the level shift output signal,and a control output of the third logic circuit or an inverted signal ofthe control output, a NOR circuit to which the second power source issupplied and which receives as inputs thereto a positively invertedsignal of the level shift input signal, an inverted signal of the levelshift output, and a control output of the third logic circuit or aninverted signal of the control output, and at least two inverters towhich the second power source is supplied and which receive as inputsthereto outputs from the respective NOR circuits, wherein each outputsignal from the inverters is produced as a control signal.
 32. A levelshifter in accordance with one of claims 24 to 27, characterized in thatthe control circuit comprises a first NOR circuit to which the secondpower source is supplied and which receives as inputs thereto aninverted signal of the level shift input signal, a positively invertedsignal of the level shift output signal, and a control output of thethird logic circuit or an inverted signal of the control output and asecond NOR circuit to which the second power source is supplied andwhich receives as inputs thereto a positively inverted signal of thelevel shift input signal, an inverted signal of the level shift output,and a control output of the third logic circuit or an inverted signal ofthe control output, wherein each output signal from the first and secondNOR circuits is produced as a control signal.
 33. A level shifter inaccordance with claim 8, characterized in that the control circuitcomprises an AND-NOR circuit to which the second power source issupplied and which receives as inputs thereto a positively invertedsignal of the level shift input signal, an inverted signal of the levelshift output signal, and a control output of the third logic circuit oran inverted signal of the control output, a NAND circuit to which thesecond power source is supplied and which receives as inputs thereto aninverted signal of the level shift input signal, a positively invertedsignal of the level shift output, and a control output of the thirdlogic circuit, and at least two inverters to which the second powersource is supplied and which receive as inputs thereto outputs from therespective NAND circuits, wherein output signals from the AND-NORcircuit, the NAND circuit, and the inverters are produced as controlsignals.
 34. A level shifter in accordance with claim 8 or 10,characterized in that the pull-up and/or pull-down circuit includes atleast two p-MOSs each of which includes a source terminal connected tothe second power source and a gate terminal connected to a controlsignal from the control circuit, a drain terminal of other p-MOS beingconnected to each of the level shift outputs and at least two n-MOSseach of which includes a source terminal connected to the GND powersource, a gate terminal connected to a control signal from the controlcircuit, and a drain terminal connected to the level shift outputs. 35.A level shifter in accordance with claim 8, characterized in that thecontrol circuit comprises an AND-NOR circuit to which the second powersource is supplied and which receives as inputs thereto a positivelyinverted signal of the level shift input signal, an inverted signal ofthe level shift output signal, and a control output of the third logiccircuit or an inverted signal of the control output and a NAND circuitto which the second power source is supplied and which receives asinputs thereto an inverted signal of the level shift input signal, apositively inverted signal of the level shift output, and a controloutput of the third logic circuit, wherein respective output signalsfrom the AND-NOR circuit and the NAND circuit are produced as controlsignals.
 36. A level shifter in accordance with claim 35, characterizedin that the pull- up and/or pull-down circuit includes at least twop-MOSs each of which includes a source terminal connected to the secondpower source and a gate terminal connected to a control signal from thecontrol circuit, a drain terminal of other p-MOS being connected to eachof the level shift outputs.
 37. A level shifter in accordance with claim8, characterized in that the control circuit comprises an AND-NORcircuit to which the second power source is supplied and which receivesas inputs thereto a positively inverted signal of the level shift inputsignal, an inverted signal of the level shift output signal, and acontrol output of the third logic circuit or an inverted signal of thecontrol output, a NAND circuit to which the second power source issupplied and which receives as inputs thereto an inverted signal of thelevel shift input signal, a positively inverted signal of the levelshift output, and a control output of the third logic circuit, and atleast two inverters to which the second power source is supplied andwhich receive as inputs thereto outputs from the respective NANDcircuits, wherein each output signal from the inverters is produced as acontrol signal.
 38. A level shifter in accordance with claim 37,characterized in that the pull- up and/or pull-down circuit includes atleast two n-MOSs each of which includes a source terminal connected tothe GND power source, a gate terminal connected to a control signal fromthe control circuit, and a drain terminal connected to the level shiftoutputs.
 39. A level shifter in accordance with claim 34, characterizedin that the control circuit comprises an OR-NAND circuit to which thesecond power source is supplied and which receives as inputs thereto aninverted signal of the level shift input signal, a positively invertedsignal of the level shift output signal, and a control output of thethird logic circuit, a NOR circuit to which the second power source issupplied and which receives as inputs thereto a positively invertedsignal of the level shift input signal, an inverted signal of the levelshift output, and a control output of the third logic circuit or aninverted signal of the control output, and at least two inverters towhich the second power source is supplied and which receive as inputsthereto outputs from the each of the NOR circuits, wherein each outputsignal from the OR-NAND circuit, the NOR circuits, and the inverters isproduced as a control signal.
 40. A level shifter in accordance withclaim 39, characterized in that the OR- NAND circuit is of a CMOScircuit configuration and a p-MOS to which the level shift input signalis connected has at least one condition that the p-MOS has a small ratioof a channel width/a channel length or a threshold value which is of anegative polarity and which is a large absolute value.
 41. A levelshifter in accordance with claim 39, characterized in that the OR- NANDcircuit is of a CMOS circuit configuration and a control signal from thethird logic circuit is connected to an n-MOS on a GND power source side.42. A level shifter in accordance with claim 36, characterized in thatthe control circuit comprises an OR-NAND circuit to which the secondpower source is supplied and which receives as inputs thereto aninverted signal of the level shift input signal, a positively invertedsignal of the level shift output signal, and a control output of thethird logic circuit, a NOR circuit to which the second power source issupplied and which receives as inputs thereto a positively invertedsignal of the level shift input signal, an inverted signal of the levelshift output, and a control output of the third logic circuit or aninverted signal of the control output, and at least two inverters towhich the second power source is supplied and which receive as inputsthereto outputs from the respective NOR circuits, wherein each outputsignal from the inverters is produced as a control signal.
 43. A levelshifter in accordance with claim 38, characterized in that the controlcircuit comprises an OR-NAND circuit to which the second power source issupplied and which receives as inputs thereto an inverted signal of thelevel shift input signal, a positively inverted signal of the levelshift output signal, and a control output of the third logic circuit anda NOR circuit to which the second power source is supplied and whichreceives as inputs thereto a positively inverted signal of the levelshift input signal, an inverted signal of the level shift output, and acontrol output of the third logic circuit or an inverted signal of thecontrol output, wherein each output signal from the OR-NAND circuit andthe NOR circuit is produced as a control signal.
 44. A level shifter inaccordance with claim 36, characterized in that the control circuitcomprises an AND-NOR circuit to which the second power source issupplied and which receives as inputs thereto a positively invertedsignal of the level shift input signal, an inverted signal of the levelshift output signal, and a control output of the third logic circuit oran inverted signal of the control output and an AND-NOR circuit to whichthe second power source is supplied and which receives as inputs theretoan inverted signal of the level shift input signal, a positivelyinverted signal of the level shift output, and a control output of thethird logic circuit or an inverted signal of the control output, whereineach output signal from the AND-NOR circuits is produced as a controlsignal.
 45. A level shifter in accordance with claim 36, characterizedin that the control circuit comprises an OR-NAND circuit to which thesecond power source is supplied and which receives as inputs thereto aninverted signal of the level shift input signal, a positively invertedsignal of the level shift output signal, and a control output of thethird logic circuit, an OR-NAND circuit to which the second power sourceis supplied and which receives as inputs thereto a positively invertedsignal of the level shift input signal, an inverted signal of the levelshift output, and a control output of the third logic circuit, and atleast two inverters to which the second power source is supplied andwhich receive as inputs thereto outputs from the respective OR-NANDcircuits, wherein each output signal from the inverters is produced as acontrol signal.
 46. A level shifter in accordance with claim 38,characterized in that the control circuit comprises an AND-NOR circuitto which the second power source is supplied and which receives asinputs thereto a positively inverted signal of the level shift inputsignal, an inverted signal of the level shift output signal, and acontrol output of the third logic circuit or an inverted signal of thecontrol output, an AND-NOR circuit to which the second power source issupplied and which receives as inputs thereto an inverted signal of thelevel shift input signal, a positively inverted signal of the levelshift output, and a control output of the third logic circuit or aninverted signal of the control output, and at least two inverters towhich the second power source is supplied and which receive as inputsthereto outputs from the respective AND-NOR circuits, wherein eachoutput signal from the inverters is produced as a control signal.
 47. Alevel converting circuit in accordance with claim 38, characterized inthat the control circuit comprises an OR-NAND circuit to which thesecond power source is supplied and which receives as inputs thereto aninverted signal of the level conversion input signal, a positivelyinverted signal of the level conversion output signal, and a controloutput of the third logic circuit and an OR-NAND circuit to which thesecond power source is supplied and which receives as inputs thereto apositively inverted signal of the level conversion input signal, aninverted signal of the level conversion output, and a control output ofthe third logic circuit, wherein each output signal from the ORNANDcircuits is produced as a control signal.
 48. A level converting circuitin accordance with claim 47, characterized in that the level conversioncore circuit comprises a p-MOS cross-coupled latch including at leasttwo of the pMOS in which each source terminal is connected to the secondsource and a gate terminal of other p-MOS is connected to each of thelevel conversion outputs, at least two p-NIOS switches including asource terminal connected to a drain terminal of the p- MOS, each gateterminal connected to a control signal from the control circuit, andeach drain terminal connected to the level conversion outputs, and adifferential n-MOS switch including at least two n-MOS each of whichincludes a source terminal connected to a GND power source, a drainterminal connected to the respective level conversion outputs, and agate terminal connected to a level conversion input.
 49. A levelconverting circuit in accordance with one of claims 11, 12, 13, 14, 19,20, 21, 22, 24, 25, 26 or 27, characterized in that the control circuitcomprises a first NAND circuit to which the second power source issupplied and which receives as inputs thereto a positively invertedsignal of the level conversion input signal, an inverted signal of thelevel conversion output signal. and a control output of the third logiccircuit, a second NAND circuit to which the second power source issupplied and which receives as inputs thereto an inverted signal of thelevel conversion input signal, a positively inverted signal of the levelconversion output, and a control output of the third logic circuit, andat least two inverters to which the second power source is supplied andwhich receive as inputs thereto outputs from the respective NANDcircuits, wherein each output signal from the first and second NANDcircuits and the at least two inverters is produced as a pull-up and/orpull-down control signal and each output signal of the inverters isproduced as a control signal of the level conversion core circuit.
 50. Alevel converting circuit in accordance with one of claims 11, 12, 13,14, 19, 20, 21, 22, 24, 25, 26 or 27 characterized in that the controlcircuit comprises a NOR circuit to which the second power source issupplied and which receives as inputs thereto an inverted signal of thelevel conversion input signal, a positively inverted signal of the levelconversion output signal, and a control output of the third logiccircuit or an inverted signal of the control output, a NOR circuit towhich the second power source is supplied and which receives as inputsthereto a positively inverted signal of the level conversion inputsignal, an inverted signal of the level conversion output, and a controloutput of the third logic circuit or an inverted signal of the controloutput, and at least two inverters to which the second power source issupplied and which respectively receive as inputs thereto outputs fromthe respective NOR circuits, wherein each output signal from the NORcircuits and the inverters is produced as a pull-up and/or pull-downcontrol signal and each output signal of the NOR circuits is produced asa control signal of the level conversion core circuit.
 51. (canceled)52. A level shifter in accordance with claim 34, characterized in thatthe control circuit comprises an AND-NOR circuit to which the secondpower source is supplied and which receives as inputs thereto apositively inverted signal of the level shift input signal, an invertedsignal of the level shift output signal, and a control output of thethird logic circuit or an inverted signal of the control output, a NANDcircuit to which the second power source is supplied and which receivesas inputs thereto an inverted signal of the level shift input signal, apositively inverted signal of the level shift output, and a controloutput of the third logic circuit, and at least two inverters to whichthe second power source is supplied and which receive as inputs theretooutputs from the respective NAND circuits, wherein each output signalfrom the AND-NOR circuit, the NAND circuit, and the at least twoinverters is produced as a pull-up and/or pull-down control signal andeach output signal of the inverters is produced as a control signal ofthe level shift core circuit.
 53. A level shifter in accordance withclaim 39, characterized in that each output signal from the OR-NANDcircuit, the NOR circuit, and the inverters is produced as a pull-upand/or pull-down control signal and each output signal of the OR-NANDcircuit and the NOR circuit is produced as a control signal of the levelshift core circuit.
 54. A level shifter in accordance with claim 8,characterized in that the control circuit comprises a first AND-NORcircuit to which the second power source is supplied and which receivesas inputs thereto a positively inverted signal of the level shift inputsignal, an inverted signal of the level shift output signal, and acontrol output of the third logic circuit or an inverted signal of thecontrol output, a second AND-NOR circuit to which the second powersource is supplied and which receives as inputs thereto an invertedsignal of the level shift input signal, a positively inverted signal ofthe level shift output, and a control output of the third logic circuitor an inverted signal of the control output, and at least two invertersto which the second power source is supplied and which receive as inputsthereto outputs from the first and second AND-NOR circuits, wherein eachoutput signal from the first and second AND-NOR circuits is produced asa pull-up and/or pull-down control signal and each output signal of theinverters is produced as a control signal of the level shift corecircuit, and the pull-up and/or pull-down circuit includes at least twop-MOSs each of which includes a source terminal connected to the secondpower source and a gate terminal connected to a control signal from thecontrol circuit, a drain terminal of other p-MOS being connected to eachof the level shift outputs.
 55. A level shifter in accordance with claim8, characterized in that the control circuit comprises a first OR-NANDcircuit to which the second power source is supplied and which receivesas inputs thereto an inverted signal of the level shift input signal, apositively inverted signal of the level shift output signal, and acontrol output of the third logic circuit, a second OR-NAND circuit towhich the second power source is supplied and which receives as inputsthereto a positively inverted signal of the level shift input signal, aninverted signal of the level shift output, and a control output of thethird logic circuit, and at least two inverters to which the secondpower source is supplied and which receive as inputs thereto outputsfrom the first and second OR-NAND circuits, wherein each output signalfrom the at least two inverters is produced as a pull-up and/orpull-down control signal and each output signal from the OR- NANDcircuits is produced as a control signal of the level shift corecircuit, and the pull-up and/or pull-down circuit includes at least twop-MOSs each of which includes a source terminal connected to the secondpower source and a gate terminal connected to a control signal from thecontrol circuit, a drain terminal of other p-MOS being connected to eachof the level shift outputs.
 56. A level converting circuit in accordancewith one of claims 5 to 8, characterized in that the control circuitcomprises an AND-NOR circuit to which the second power source issupplied and which receives as inputs thereto a positively invertedsignal of the level conversion input signal, an inverted signal of thelevel conversion output signal, and a control output of the third logiccircuit or an inverted signal of the control output, an AND-NOR circuitto which the second power source is supplied and which receives asinputs thereto an inverted signal of the level conversion input signal,a positively inverted signal of the level conversion output, and acontrol output of the third logic circuit or an inverted signal of thecontrol output, and at least two inverters to which the second powersource is supplied and which receive as inputs thereto outputs from therespective AND-NOR circuits. wherein each output signal from theinverters is produced as a pull-up and/or pull-down control signal, eachoutput signal from the inverters is produced as a control signal of thelevel conversion core circuit, and the pull-up and/or pull-down circuitincludes at least two n-MOS each of which includes a source terminalconnected to the GND power source, a gate terminal connected to acontrol signal from the control circuit, and a drain terminal connectedto the level conversion outputs.
 57. A level converting circuit inaccordance with one of claims 5 to 8, characterized in that the controlcircuit comprises a first OR-NAND circuit to which the second powersource is supplied and which receives as inputs thereto an invertedsignal of the level conversion input signal, a positively invertedsignal of the level conversion output signal, and a control output ofthe third logic circuit and a second OR-NAND circuit to which the secondpower source is supplied and which receives as inputs thereto apositively inverted signal of the level conversion input signal, aninverted signal of the level conversion output, and a control output ofthe third logic circuit, wherein each output signal from the first andsecond OR- NAND circuits is produced as a pull-up and/or pull-downcontrol signal, each output signal from the OR-NAND circuits is producedas a control signal of the level conversion core circuit, and thepull-up and/or pull-down circuit includes at least two n-VIOS each ofwhich includes a source terminal connected to the GND power source, agate terminal connected to a control signal from the control circuit,and a drain terminal connected to the level conversion outputs.
 58. Alevel converting circuit in accordance with one of claims 5 to 8,characterized in that the control circuit comprises an AND-NOR circuitto which the second power source is supplied and which receives asinputs thereto a positively inverted signal of the level conversioninput signal, an inverted signal of the level conversion output signal,and a control output of the third logic circuit or an inverted signal ofthe control output, an AND-NOR circuit to which the second power sourceis supplied and which receives as inputs thereto an inverted signal ofthe level conversion input signal, a positively inverted signal of thelevel conversion output, and a control output of the third logic circuitor an inverted signal of the control output, and at least two invertersto which the second power source is supplied and which receive as inputsthereto outputs from the respective AND-NOR circuits, wherein eachoutput signal of the inverters is produced as a control signal of thelevel conversion core circuit.
 59. A level converting circuit inaccordance with one of claims 5, 6, 7, 10, 11, 12, 13 or 14,characterized in that the control circuit comprises an OR-NAND circuitto which the second power source is supplied and which receives asinputs thereto an inverted signal of the level conversion input signal,a positively inverted signal of the level conversion output signal, anda control output of the third logic circuit and an OR-:‘NAND circuit towhich the second power source is supplied and which receives as inputsthereto a positively inverted signal of the level conversion inputsignal, an inverted signal of the i.evel conversion output, and acontrol output of the third logic circuit, wherein each output signalfrom the OR-NAND circuits is produced as a control signal of the levelconversion core circuit.
 60. A level converting circuit in accordancewith one of claims 1 or 8, characterized in that: the level conversioncore circuit comprises a p-BIOS crosscoupled latch including at leasttwo first p-MOS. a differential n-MOS including at least two n-MOS, andat least two second p- MOS, wherein: the p-MOS cross-coupled latchincludes a source terminal connected to the second power source and agate terminal connected to a level conversion output which is each drainterminal of the second pMOS; the differential n-MOS includes each sourceterminal connected to the GND power source, each drain terminalconnected to the level conversion output, and each gate terminalconnected to a level conversion input; and the second p-MOS includeseach source terminal connected of the first p-MOS, each gate terminalconnected to the level conversion input, and each drain terminalconnected to the ‘level conversion output.
 61. A level convertingcircuit for converting a signal level of a first logic circuit to whicha first power source is supplied into a signal level of a second logiccircuit to which a second power source is supplied, characterized byincluding a pull-down circuit at a level conversion output of a levelconversion core circuit and a control circuit to which the second powersource supplied and which receives as inputs thereto a level conversioninput signal the level conversion output signal to produce controlsignals for a pull-down circuit and a level conversion core circuit,wherein the control circuit is also connected to control signals fromthe third logic circuit.
 62. A level converting circuit in accordancewith claim 61, characterized in that the control circuit, the controlcircuit comprises a first OR-NAND circuit to which the second powersource is supplied and which receives as inputs thereto an invertedsignal of the level conversion input signal, a positively invertedsignal of the level conversion output signal, and a control output ofthe third logic circuit and a second OR-NAND circuit to which the secondpower source is supplied and which receives as inputs thereto apositively inverted signal of the level conversion input signal, aninverted signal of the level conversion output, and a control output ofthe third logic circuit, wherein each output signal from the first andsecond OR- NAND circuits is produced as a pull-up and/or pull-downcontrol signal, each output signal from the OR-NAND circuits is producedas a control signal of the level conversion core circuit, and thepull-down circuit, the pull-up and/or pull-down circuit include at leasttwo n-MOS each of which includes a source terminal connected to the GNDpower source, a gate terminal connected to a control signal from thecontrol circuit, and a drain terminal connected to the level conversionoutputs.
 63. A level converting circuit in accordance with claim 61,characterized in that the control circuit, the control circuit comprisesa first OR-NAND circuit to which the second power source is supplied andwhich receives as inputs thereto an inverted signal of the levelconversion input signal, a positively inverted signal of the levelconversion output signal. and a control output of the third Logiccircuit and a second OR-NAND circuit to which the second power source issupplied and which receives as inputs thereto a positively invertedsignal of the level conversion input signal, an inverted signal of thelevel conversion output, and a control output of the third logic circuitor an inverted signal of the control output, wherein each output signalfrom the first and second OR-NAND circuits is produced as a pull-upand/or pull- down control signal, each output signal from the OR-NANDcircuits is produced as a control signal of the level conversion corecircuit, and the pull-down circuit, the pull-up and/or pull-down circuitinclude at least two n-MOS each of which includes a source terminalconnected to the GND power source, a gate terminal connected to acontrol signal from the control circuit, and a drain terminal connectedto the level conversion outputs.
 64. (canceled)
 65. A level shifter inaccordance with one of claims 5, 6 or 61, characterized in that thecontrol circuit comprises at least two NOR circuits to which the secondpower source is supplied and which receives as inputs thereto aninverted signal of the level shift input signal, a positively invertedsignal of the level shift output signal, and a control output of thethird logic circuit or an inverted signal of the control output and aNOR circuit to which the second power source is supplied and whichreceives as inputs thereto a positively inverted signal of the levelshift input signal, an inverted signal of the level shift output, and acontrol output of the third logic circuit or an inverted signal of thecontrol output, wherein each output signal from the NOR circuits isproduced as a control signal of the level shift core circuit.
 66. Alevel shifter in accordance with one of claims 11, 12, or 61,characterized in that the control circuit comprises at least two NANDcircuits to which the second power source is supplied and which receivesas inputs thereto a positively inverted signal of the level shift inputsignal, an inverted signal of the level shift output signal, and acontrol output of the third logic circuit, a NAND circuit to which thesecond power source is supplied and which receives as inputs thereto aninverted signal of the level shift input signal, a positively invertedsignal of the level shift output signal, and a control output of thethird logic circuit, and at least two inverters to which the secondpower source is supplied and which receives as inputs thereto outputsfrom the respective NAND circuits, wherein each output signal from theinverters is produced as a control signal of the level shift corecircuit.